Renesas Electronics - United States, Engineering

Lead system-level power solutions for AI servers as a Power System Application Engineer in Plano. Requires 5+ years in power electronics, DC-DC converters, and IC definition. Drive 48V IBC innovation with cross-functional teams.

Lead verification strategy for next-gen DDR6 semiconductor memory interfaces in Duluth. Requires deep SystemVerilog and UVM expertise, technical ownership of complex verification efforts, and collaboration with RTL design teams. DDR experience a plus.

Lead verification strategy for next-gen DDR6 semiconductor memory interfaces in Chandler. Requires deep SystemVerilog and UVM expertise, technical ownership of complex verification efforts, and strong collaboration with RTL design teams.

Lead verification strategy for next-gen DDR6 memory interface products in San Jose. Requires deep SystemVerilog and UVM expertise, technical ownership of complex semiconductor verification, and close collaboration with RTL teams.

Lead advanced semiconductor packaging development at Renesas in San Jose. Requires MSc/PhD, 5+ years packaging experience, and expertise in WLP, 2.5D/3D, SiP, and flip-chip technologies.

Lead the architectural evolution of PMIC and mixed-signal products as a global technical authority in Chandler. Requires 12+ years in power management, CMOS expertise, and proven technical leadership on complex ICs.

Lead mixed-signal verification for PMICs, chargers and switching regulators in Chandler. Requires 8-12+ years with AMS/DMS, SystemVerilog, UVM, Verilog-AMS and Cadence tools. Drive chip-level sign-off and behavioral modeling.

Lead analog and mixed-signal IC development at Renesas in San Jose. Requires MSEE, 15+ years in precision analog and power management design, plus strong leadership and mentoring skills.

Lead analog and mixed-signal IC development at Renesas in Austin. Requires MSEE, 15+ years of precision analog and power management design experience, plus strong team mentoring and cross-functional collaboration skills.

Renesas seeks a Senior Staff Design Verification Engineer in Duluth to lead verification of advanced memory interface products for data center and AI. Requires 10+ years in semiconductor verification, SystemVerilog and UVM expertise.