Renesas Electronics - United States, Engineering

Lead analog design for complex power management ICs in Chandler. Guide a team, drive innovation, and represent Dialog to customers. Requires 5-10+ years analog design experience and a B.S./M.S. in EE or related field.

Renesas seeks a Staff Digital Mixed-Signal Systems Engineer in Austin to develop and verify digital data paths for next-gen power management in AI and datacenter applications. Requires 5+ years experience and strong DSP skills.

Seeking a Field Applications Engineer in Boston to drive design-ins for Renesas embedded processing products. Requires 5+ years of ARM/MCU design experience and strong customer-facing technical skills.

Lead package technology development for AI and data center power products at Renesas in Tempe. Requires 12-15 years of semiconductor packaging experience and expertise in SiP, wafer-level, and flip-chip packaging.

Join Renesas in Austin as a Senior Power Management Applications Engineer. Drive adoption of DC-DC and multiphase power solutions, support tier-1 customer designs, and define next-gen power ICs. Hands-on DC/DC conversion expertise required.

Lead post-silicon validation for DDR5 memory in Duluth. Requires 8+ years in high-speed analog/mixed-signal testing, BERT/scope expertise, Python scripting, and strong signal integrity knowledge. Drive silicon bring-up and debug.

Renesas seeks a Principal Analog IC Designer in Morrisville, NC to join its Rad Hard IC team. Requires deep expertise in power management, BCD/BiCMOS processes, and Cadence tools. Drive innovative power products from concept to production.

Lead verification strategy for next-gen DDR6 semiconductor memory interfaces in Plano. Requires deep SystemVerilog and UVM expertise, technical ownership of complex verification efforts, and strong collaboration with RTL design teams.

Renesas seeks a Staff Package Design Engineer in Tempe, AZ to design advanced packages (FCBGA, SiP, WLCSP, power modules). Requires 4+ years CAD layout experience and strong OSAT/substrate collaboration skills.

Lead analog design for complex power management ICs in Chandler. Guide team members on best practices, drive improvements, and represent the company to external customers. Requires 5-10+ years analog design experience and B.S./M.S. in EE.

Lead semiconductor process and device development as Principal Electrical Engineer in San Jose. Requires MS/PhD, 10+ years in CMOS/BCD integration, foundry collaboration, and test-chip tape-out expertise.

Lead verification strategy for next-gen DDR6 semiconductor memory interfaces in Austin. Requires deep SystemVerilog and UVM expertise, technical ownership of complex verification efforts, and collaboration with RTL teams. DDR experience a plus.