Renesas Electronics - United States, Engineering

Join our San Jose team as an Application Engineer Intern for Summer 2027, focusing on DDR5 power validation and optimization. Requires analog circuit knowledge, LabVIEW/Python skills, and hands-on lab experience.

Renesas seeks a Senior Reliability Engineer in Goleta to drive qualification and reliability assessment of advanced power semiconductors. Requires expertise in device physics, accelerated life testing, and failure mechanisms. GaN experience preferred.

Principal Analog Design Engineer in Duluth to architect and verify CMOS analog blocks for custom ASICs. Requires 10-15 years of analog design experience and DDR5/DDR6 I/O expertise.

Lead system-level power solutions for AI servers in Plano. Define 48V IBC products, IC requirements, and validation plans. Requires 5+ years in power electronics, DC-DC expertise, and strong cross-functional leadership.

Lead ATE test strategy for high-performance AI power solutions in San Jose. Requires 10+ years semiconductor experience, V93K/Diamondx expertise, and mixed-signal IC mastery. Define roadmaps and drive global production release.

Renesas seeks a Principal Digital Design Engineer in San Jose to lead SOC architecture and RTL development. Requires 8+ years experience, strong protocol knowledge, and offers a dynamic, multicultural environment.

Staff Application Engineer in San Jose to validate USB high-speed interfaces and memory systems. Requires 7+ years in power management or USB compliance testing, bench validation skills, and automation experience.

Senior Application Engineer for DDR5 power management and PMIC sought in San Jose. Requires 4+ years in power management or memory design, bench validation skills, and LabVIEW/Python automation. Drive validation and optimization of DDR5 memory systems.

Renesas seeks a Principal ESD Engineer in Chandler to lead ESD methodology, custom IP development, and sign-off verification for FinFET SoCs and SerDes. Requires 10+ years of ESD design expertise and strong leadership skills.

Lead PMIC and mixed-signal architecture at a global innovator in Plano. Requires 8-10 years in power management, CMOS expertise, and technical leadership. Mentor teams and shape product roadmaps.

Senior Staff Analog Engineer in Chandler to lead PMIC and mixed-signal architecture across the full lifecycle. Requires 8-10 years in power management, CMOS expertise, and proven technical leadership with strong mentoring skills.

Renesas seeks an entry-level Electrical Engineer in Duluth, GA (hybrid) to verify DDR5/DDR6 memory interface chips for AI and cloud datacenters. Requires a BSc with up to 2 years experience or a recent master's grad.