Renesas Electronics - United States, Engineering

Lead post-silicon validation for DDR5 memory buffers in Duluth. Requires 8+ years in high-speed analog/mixed-signal characterization, BERT/scope expertise, Python scripting, and strong signal integrity knowledge.

Senior Staff Test Engineer in Austin to develop ATE test programs for analog, digital and mixed-signal products. Requires 10-15+ years of ATE experience, C++/Python skills and strong analog power testing expertise.

Senior Power Electronics Test Engineer needed in Goleta to validate GaN power devices through SALT/HTOL test circuits, MCU firmware development, and power converter analysis. Requires EE degree, 5+ years experience, and C/C++ proficiency.

Experienced Product Engineer needed in Tempe to own advanced power module manufacturability from NPI through high-volume production. Requires 8+ years in semiconductor product engineering and strong technical depth in power module assembly.

Lead DC-DC power product definition for industrial and enterprise server markets at Renesas in Plano. Hands-on technical leadership role driving customer engagement, product roadmaps, and system-level power solutions. Requires 15+ years in power electronics.

Senior Staff Device Characterization Engineer in Palm Bay to lead power device testing and lab development. Requires 10+ years in semiconductor characterization, Python/MATLAB skills, and expertise with automated probers and parameter analyzers.

Experienced Staff Application Engineer needed in San Jose to drive USB protocol validation and memory system optimization. Requires 7+ years in power management or memory design, bench validation expertise, and automation skills.

Lead system-level power solutions for AI servers as a Power System Application Engineer in Plano. Requires 5+ years in power electronics, DC-DC converters, and IC definition. Drive 48V IBC innovation.

Entry-level Validation Engineer role in Duluth, GA for recent Master's graduates in EE or Computer Engineering. Hands-on silicon validation work with DDR, memory controllers, and lab equipment. Requires Python/C/C++ skills and strong circuit knowledge.

Renesas seeks a Principal Digital Design Engineer in San Jose to lead SOC architecture and RTL design. Requires MSEE/PhD with 8+ years experience, strong protocol knowledge, and AI-savvy mindset.

Senior Application Engineer for DDR5 power management and PMIC sought in San Jose. Requires 4+ years in power management or memory design, bench validation skills, and LabVIEW/Python automation. Drive validation and optimization of DDR5 memory systems.

Renesas seeks a Senior Reliability Engineer in Goleta to drive reliability assessment of advanced power semiconductors. Requires expertise in device physics, accelerated life testing, and failure mechanisms. GaN experience strongly preferred.