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Design Verification Engineer Jobs

70 Job Offers

ASIC Engineer, Design Verification
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Asic Engineer, Design Verification
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Design Verification Engineer
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Join AMD in Vancouver, Canada as a Design Verification Engineer to shape next-gen computing. You'll develop UVM testbenches, write SystemVerilog test cases, and analyze coverage for AI and data center products. Ideal candidates hold a Master’s or Bachelor’s in electrical/computer engineering with...
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105600.00 - 158400.00 CAD / Year
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Sr ASIC Design Verification Engineer (NetSec)
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Join a top-tier ASIC team in Santa Clara as a Sr Design Verification Engineer, driving next-gen firewall ASICs from concept to mass production. Leverage SystemVerilog and UVM to architect test benches, define coverage, and debug across simulation, emulation, and formal verification. Ideal candida...
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Design Verification Engineer - Machine Learning Accelerators
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Join Meta's Reality Labs as a Design Verification Engineer in Sunnyvale, CA, driving cutting-edge Machine Learning Accelerators for AR and smart devices. Leverage 10+ years of SystemVerilog/UVM and C/C++ expertise to lead IP and SoC verification, ensuring first-pass silicon success. Collaborate o...
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178000.00 - 250000.00 USD / Year
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Principal Silicon Design Verification Engineer
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Principal Silicon Design Verification Engineer sought to validate cutting-edge DPU silicon in Santa Clara. You will lead pre-silicon SoC verification using UVM/C, develop test plans, and debug complex designs for datacenter solutions. Requires a Doctorate or Master’s in EE/CE with 3-6+ years of e...
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142800.00 - 304200.00 USD / Year
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Design Verification Engineer
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AMD in Markham, Canada seeks a Design Verification Engineer to plan, build, and execute verification for graphics processor IP. You will develop UVM-based frameworks, debug RTL/firmware, and drive coverage closure using SystemVerilog, C++, and Perl/Python. Ideal candidates hold a Bachelors/Master...
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128000.00 - 192000.00 CAD / Year
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Senior Design Verification Engineer
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Senior Design Verification Engineer at Microsoft Silicon in Mountain View, CA. Drive pre-silicon functional verification for cloud infrastructure powering Azure, Bing, and Office 365. Requires expertise in Verilog, C/C++, Python, and developing complex test environments. Join a world-class team d...
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119800.00 - 261000.00 USD / Year
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Principal Quantum Design Verification Engineer
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Join Microsoft Quantum in Redmond as a Principal Quantum Design Verification Engineer to drive scalable, fault-tolerant quantum computing. You will own verification environments for complex SoC and IP designs, leveraging UVM, SystemVerilog, and AMS models. Requires a Doctorate or equivalent exper...
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139900.00 - 274800.00 USD / Year
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Senior Quantum Design Verification Engineer
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Senior Quantum Design Verification Engineer sought by Microsoft in Redmond, WA. Drive pre-silicon simulation and post-silicon validation for cutting-edge quantum SoCs. Requires a Doctorate/Master’s/Bachelor’s in Physics or Engineering with industry experience. Own verification environments, test ...
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119800.00 - 234700.00 USD / Year
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About the Design Verification Engineer role

Design Verification Engineer jobs represent a critical pillar in the semiconductor and hardware development industry, ensuring that complex integrated circuits and systems-on-chip (SoCs) function correctly before they are manufactured. Professionals in this role act as the quality gatekeepers of the digital design world, tasked with the rigorous process of confirming that a design meets its specified requirements and operates without critical bugs. The primary responsibility of a Design Verification Engineer is to create and execute comprehensive verification plans. This involves developing sophisticated testbenches using industry-standard methodologies like Universal Verification Methodology (UVM) and languages such as SystemVerilog, Verilog, and C++.

They write both directed and constrained-random tests to stress-test the design, simulating millions of possible scenarios to uncover hidden flaws. A significant part of the daily work involves debugging test failures, working closely with RTL designers to identify whether a bug lies in the design itself or in the test environment. They use advanced simulation tools to analyze waveforms and trace logic errors, ensuring that every functional corner case is covered. Coverage analysis is another core duty; engineers must track code coverage and functional coverage metrics to guarantee that no part of the design remains untested.

This often requires modifying tests or adding new ones to meet strict coverage goals. Beyond pre-silicon simulation, many Design Verification Engineer jobs involve post-silicon validation, where they help bring up actual silicon in the lab, running tests on real hardware to ensure it matches simulation results. They also work with emulation platforms to run software workloads at higher speeds, bridging the gap between simulation and final production. Collaboration is essential, as these engineers interface daily with architects, design engineers, firmware teams, and design-for-test (DFT) specialists to align verification strategies and resolve issues early in the development cycle.

Typical skills required for these roles include deep proficiency in SystemVerilog and UVM, strong debugging abilities, and experience with scripting languages like Perl, Python, or Makefile for automation. A solid understanding of digital logic design, computer architecture, and protocols is also crucial. Most positions require a Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field, coupled with several years of hands-on verification experience. As chips grow more complex—integrating AI accelerators, advanced graphics, and high-speed interfaces—the demand for meticulous and innovative Design Verification Engineer jobs continues to rise, making this profession indispensable for delivering reliable, high-performance silicon to market.