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Design Verification Engineer Jobs

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Design Verification Engineer
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Join AMD's team in Santa Clara as a Design Verification Engineer. You will verify complex DDR memory subsystems using SystemVerilog, UVM, and C/C++. Collaborate with cross-functional teams to ensure the highest quality IP and drive coverage closure for industry-leading technologies.
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United States , Santa Clara
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Salary
200000.00 - 300000.00 USD / Year
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AMD
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ASIC Engineer, Design Verification
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Join Meta's cutting-edge hardware team as an ASIC Design Verification Engineer in Austin. You will verify complex IP/SoC designs using SystemVerilog/UVM and Python/TCL scripting. This role requires a Bachelor's degree and 1+ year of experience in UVM-based verification. We offer a competitive pac...
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United States , Austin
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132198.00 - 162580.00 USD / Year
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Meta
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Senior Silicon Design Verification Engineer
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Lead the verification of cutting-edge Crypto, NoC, and DRAM Memory Controller IPs (LPDDR6/HBM4) at Intel's AECG in San Jose. Utilize advanced UVM, SystemVerilog, and formal verification to ensure first-pass silicon success. This senior role requires technical leadership of teams and expertise in ...
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United States , San Jose
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136000.00 - 204000.00 USD / Year
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AMD
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Design verification Engineer
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Join our team in Markham as a Junior Verification Engineer. You will verify AMD's PCIe BFM using UVM testbenches and PIPE mode, focusing on protocol compliance and data integrity. This role is ideal for a new graduate eager to learn PCIe protocol and advanced verification methodologies in a colla...
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Canada , Markham
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Salary
103200.00 - 154800.00 CAD / Year
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AMD
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Design Verification Engineer
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Join AMD's Infinity Fabric team in Bangalore as a Design Verification Engineer. Utilize your 7+ years of formal verification expertise on complex IPs to verify configurable switches and die-to-die interconnects. You will create testbenches, mentor junior engineers, and work on cutting-edge produc...
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India , Bangalore
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Not provided
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AMD
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Silicon Design Verification Engineer
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Join AMD/Xilinx as a Silicon Design Verification Engineer in San Jose. You will verify next-gen programmable devices using SystemVerilog, UVM, and advanced methodologies. This role requires expertise in computer architecture, C/C++, and Python scripting. Collaborate globally to drive verification...
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United States , San Jose
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Salary
159840.00 - 239760.00 USD / Year
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AMD
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ASIC Engineer, Design Verification
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Join Meta's cutting-edge hardware team as an ASIC Design Verification Engineer in Sunnyvale. You will develop verification plans, build testbenches using SystemVerilog/UVM, and ensure design quality for next-gen technologies. This role requires a Master's and 2+ years of experience in ASIC verifi...
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United States , Sunnyvale
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149000.00 - 162580.00 USD / Year
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Meta
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Principal Design Verification Engineer
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Join Microsoft's Silicon Engineering team in Raleigh as a Principal Design Verification Engineer. You will lead verification for complex Fabric Interconnect subsystems using advanced UVM methodologies. This role requires 5+ years of pre-silicon verification experience and offers the chance to inn...
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United States , Raleigh
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139900.00 - 274800.00 USD / Year
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Microsoft Corporation
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Staff Software Engineer, Model Based Design and Verification
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Join Archer's MBD Software Team in São Paulo as a Staff Software Engineer. Develop and certify safety-critical embedded software for Flight Controls or Battery Management Systems using MATLAB/Simulink and C/C++. This role requires 8+ years' experience with DO-178C/DO-331 standards and model-based...
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Brazil , São Paulo
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Not provided
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Archer Aviation
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ASIC Engineer, Design Verification
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United States , Sunnyvale
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186000.00 - 192170.00 USD / Year
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Meta
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Design Verification Engineer
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Join Meta's cutting-edge hardware team in Sunnyvale as a Design Verification Engineer. You will verify complex SoC/IP blocks using SystemVerilog, UVM, and Python. This role requires a Master's in EE/CE/CS and hands-on verification experience. We offer competitive compensation including bonus and ...
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United States , Sunnyvale
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136926.00 - 162580.00 USD / Year
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Meta
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Senior Staff Silicon Design Engineer (Design Verification)
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Join AMD in Penang as a Senior Staff Silicon Design Engineer, specializing in Design Verification. You will own IP feature design and RTL delivery for mainstream products, requiring strong ASIC/SoC and Verilog skills. This role offers a collaborative culture focused on innovation in AI and next-g...
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Malaysia , Penang
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Not provided
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AMD
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Design Verification Engineer
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United States , San Francisco
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226000.00 - 445000.00 USD / Year
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OpenAI
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Design Verification Engineer - Internal IP
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Join our Internal IP DV team in San Jose as a Design Verification Engineer. You will verify high-performance custom IPs like systolic arrays and NoCs using UVM/SystemVerilog. Collaborate with architects and SW/FW teams to ensure silicon-ready designs. We offer excellent benefits including medical...
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United States , San Jose
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Salary
150000.00 - 275000.00 USD / Year
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Etched
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Design Verification Engineer - SoC
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Join our team in San Jose as a Design Verification Engineer for SoC. You will verify custom IPs like systolic arrays and NoCs, using SystemVerilog and Python. Collaborate with architects and software teams on performance validation and modeling. We offer comprehensive benefits, a housing subsidy,...
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United States , San Jose
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150000.00 - 275000.00 USD / Year
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Etched
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Senior Verification Design Engineer
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Join AMD in British Columbia as a Senior Verification Design Engineer. You will plan and execute verification for graphics IP using UVM, SystemVerilog, and C++. This role focuses on building testbenches, debugging, and ensuring coverage to achieve a bug-free design. Experience with ASIC verificat...
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Canada , BRITISH COLUMBIA
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Salary
124000.00 - 186000.00 CAD / Year
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AMD
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Design Verification Engineer - Interface IP
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Join our Interface IP DV team as a Design Verification Engineer in San Jose. Take ownership of PCIe, Ethernet, or CPU subsystems using UVM/SystemVerilog. We offer comprehensive benefits, a housing subsidy, and a collaborative, fast-paced environment.
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United States , San Jose
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Salary
150000.00 - 275000.00 USD / Year
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Etched
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ASIC Engineer, Design Verification
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Join Meta as an ASIC Design Verification Engineer in Sunnyvale. You will verify cutting-edge IP and SoCs for data centers using SystemVerilog/UVM, formal methods, and emulation. This role requires a relevant degree and 2+ years of hands-on verification experience. We offer a competitive package i...
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United States , Sunnyvale
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Salary
114000.00 - 172000.00 USD / Year
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Meta
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Design Verification Engineer
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United States , Sunnyvale
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Salary
120000.00 - 240000.00 USD / Year
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Cerebras Systems
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Asic engineer intern, design verification
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Join Meta's Infrastructure team in Bangalore as an ASIC Engineer Intern, specializing in Design Verification. You will verify advanced IPs using SystemVerilog/UVM, contributing to "Green" data center accelerators. This 12-16 week internship requires a background in Electrical/Computer Engineering...
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India , Bangalore
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Not provided
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Meta
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About the Design Verification Engineer role

Design Verification Engineer jobs represent a critical pillar in the semiconductor and hardware development industry, ensuring that complex integrated circuits and systems-on-chip (SoCs) function correctly before they are manufactured. Professionals in this role act as the quality gatekeepers of the digital design world, tasked with the rigorous process of confirming that a design meets its specified requirements and operates without critical bugs. The primary responsibility of a Design Verification Engineer is to create and execute comprehensive verification plans. This involves developing sophisticated testbenches using industry-standard methodologies like Universal Verification Methodology (UVM) and languages such as SystemVerilog, Verilog, and C++.

They write both directed and constrained-random tests to stress-test the design, simulating millions of possible scenarios to uncover hidden flaws. A significant part of the daily work involves debugging test failures, working closely with RTL designers to identify whether a bug lies in the design itself or in the test environment. They use advanced simulation tools to analyze waveforms and trace logic errors, ensuring that every functional corner case is covered. Coverage analysis is another core duty; engineers must track code coverage and functional coverage metrics to guarantee that no part of the design remains untested.

This often requires modifying tests or adding new ones to meet strict coverage goals. Beyond pre-silicon simulation, many Design Verification Engineer jobs involve post-silicon validation, where they help bring up actual silicon in the lab, running tests on real hardware to ensure it matches simulation results. They also work with emulation platforms to run software workloads at higher speeds, bridging the gap between simulation and final production. Collaboration is essential, as these engineers interface daily with architects, design engineers, firmware teams, and design-for-test (DFT) specialists to align verification strategies and resolve issues early in the development cycle.

Typical skills required for these roles include deep proficiency in SystemVerilog and UVM, strong debugging abilities, and experience with scripting languages like Perl, Python, or Makefile for automation. A solid understanding of digital logic design, computer architecture, and protocols is also crucial. Most positions require a Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field, coupled with several years of hands-on verification experience. As chips grow more complex—integrating AI accelerators, advanced graphics, and high-speed interfaces—the demand for meticulous and innovative Design Verification Engineer jobs continues to rise, making this profession indispensable for delivering reliable, high-performance silicon to market.