Staff Design Engineer Jobs

Renesas seeks a Staff Package Design Engineer in Bengaluru with 6+ years of CAD layout experience in 2.5D/3D IC, FCBGA and SiP packages. Proficiency in Cadence Allegro or Siemens Xpedition required.

Renesas seeks a Senior Staff Package Design Engineer in Suzhou to develop power SiP, wafer-level and flip-chip packaging. Requires 10+ years in package development, GaN and OSAT/CM experience.

Renesas seeks a Senior Staff Package Design Engineer in Kaohsiung to develop power SiP/module, wafer-level and flip-chip packaging. Requires 10+ years experience, GaN knowledge a plus.

Renesas seeks a Senior Staff Package Design Engineer in Taipei to develop power SiP/module, wafer-level and flip-chip packaging. Requires 10+ years of package development experience and strong GaN or power expertise.

Senior Staff Package Design Engineer role in Shanghai requiring 10+ years in power SiP/module, wafer level and flip-chip packaging. Lead OSAT/CM qualification, DOE process optimization and new package qualification for consumer, industrial and automotive power applications.

Lead cutting-edge semiconductor packaging innovation in Bayan Lepas. Design PowerQFN, Flip-Chip and SiP solutions for AI/HPC markets. Requires 5-15 years package development experience and engineering degree.

Renesas seeks a Senior Staff Package Design Engineer in Taichung to develop power SiP, wafer-level and flip-chip packaging. Requires 10+ years in package development, GaN and power module expertise, plus strong OSAT/CM collaboration skills.

Renesas seeks a Staff Package Design Engineer in Taipei to develop power SiP, wafer-level and flip-chip packaging. Requires 10+ years in package development, strong analytical skills and GaN knowledge is a plus.

Renesas seeks a Sr. Staff Engineer in Bengaluru with 10+ years of physical design experience. Drive RTL-to-GDSII, PPA optimization, and timing closure using Fusion Compiler, Innovus, and Primetime.

Renesas seeks a Sr Staff Engineer in Bengaluru to architect and deliver high-performance analog/mixed-signal IPs. Requires 10+ years of IC design experience and full lifecycle ownership from specification to silicon validation.

Renesas seeks a Staff/Principal Analog Design Engineer in Bengaluru to architect complex power-management ICs, PMICs, and mixed-signal blocks. Requires 6-15 years of analog design expertise with hands-on PMIC and converter experience.

Renesas seeks a Senior Staff Engineer in Bengaluru to architect and deliver high-performance analog/mixed-signal IPs. Requires 10+ years of IC design experience and full lifecycle ownership from specification to silicon validation.

Senior digital design role in Catania for an engineer with 8-12 years of experience and EE/ECE degree. Work on advanced power management ICs, leading RTL design, verification and automation with Verilog and SystemVerilog.

Experienced Staff Layout Design Engineer needed in Sophia Antipolis to work on DC-DC converters, controllers and drivers. Requires 6+ years in Analog Layout Design, DRC/LVS flows and full chip ownership.

Experienced Staff Mask Design Engineer needed in Chandler to lead analog and mixed-signal IC layout for automotive applications. Requires 8+ years of layout experience, advanced CMOS BCD expertise, and strong physical verification skills.

Renesas seeks a Staff Package Design Engineer in Tempe, AZ to design advanced packages (FCBGA, SiP, WLCSP, power modules). Requires 4+ years CAD layout experience and strong OSAT/substrate collaboration skills.

Lead AMS design verification at Renesas in Bengaluru. Requires 10+ years in advanced verification, UVM, SystemVerilog, and mixed-signal tools like Cadence Virtuoso and xCelium. Drive first-pass silicon success.

Renesas seeks a Staff Design Verification Engineer in Duluth to verify advanced DDR6 memory interface products for data center and AI. Requires 8+ years in semiconductor verification, strong SystemVerilog and UVM skills.

Renesas seeks a Senior Staff Design Verification Engineer in Duluth to lead verification of advanced memory interface products for data center and AI. Requires 10+ years in semiconductor verification, SystemVerilog and UVM expertise.