Principal Design Engineer Jobs

Lead HV/EHV cable system design projects at AECOM in Leeds. Requires technical leadership, National Grid TP and IEC standards expertise, and multidisciplinary team coordination. Shape sustainable infrastructure with a global team.

AECOM seeks a Principal Cable System Design Engineer in Newcastle-Upon-Tyne to lead HV/EHV cable projects from concept to completion. Requires technical leadership, National Grid standards expertise, and multidisciplinary team coordination skills.

Renesas seeks a Principal Digital Design Engineer in San Jose to lead SOC architecture and RTL design. Requires 8+ years experience, strong protocol knowledge, and offers a dynamic, multicultural environment.

Lead digital design for advanced power management ICs in Austin. Requires 10+ years EE/ECE experience, Verilog expertise, and strong debug skills. Mentor junior engineers and drive innovative chip development.

Lead verification strategy for next-gen DDR6 semiconductor memory interfaces in Plano. Requires deep SystemVerilog and UVM expertise, technical ownership of complex verification efforts, and strong collaboration with RTL design teams.

Lead verification strategy for next-gen DDR6 semiconductor memory interfaces in Austin. Requires deep SystemVerilog and UVM expertise, technical ownership of complex verification efforts, and collaboration with RTL teams. DDR experience a plus.

Lead verification strategy for next-gen DDR6 semiconductor memory interfaces in Duluth. Requires deep SystemVerilog and UVM expertise, technical ownership of complex verification efforts, and collaboration with RTL design teams. DDR experience a plus.

Lead verification strategy for next-gen DDR6 semiconductor memory interfaces in Chandler. Requires deep SystemVerilog and UVM expertise, technical ownership of complex verification efforts, and strong collaboration with RTL design teams.

Lead verification strategy for next-gen DDR6 memory interface products in San Jose. Requires deep SystemVerilog and UVM expertise, technical ownership of complex semiconductor verification, and close collaboration with RTL teams.

Lead advanced semiconductor packaging development at Renesas in San Jose. Requires MSc/PhD, 5+ years packaging experience, and expertise in WLP, 2.5D/3D, SiP, and flip-chip technologies.

Lead the architectural evolution of PMIC and mixed-signal products as a global technical authority in Chandler. Requires 12+ years in power management, CMOS expertise, and proven technical leadership on complex ICs.

Lead digital design projects for advanced power management ICs in Austin. Requires 10+ years EE/ECE experience, Verilog expertise, and strong leadership skills. Mentor junior engineers and drive innovation.

Lead digital architecture for UA Link Switch products at Renesas in Bengaluru. Requires 15+ years in digital ASIC/SoC development, RTL design, and high-speed interconnect expertise. Shape next-gen semiconductor solutions.

Renesas seeks a Principal Digital Design Engineer in Duluth to architect RTL for DDR5/DDR6 memory buffer chips powering AI and cloud data centers. Requires 12+ years of ASIC/IC design expertise and strong Verilog skills.