Principal Design Engineer Jobs

Astera Labs seeks a Principal Physical Design Engineer in Ahmedabad to drive complex SoC/silicon development for AI infrastructure. Requires 8+ years of backend experience with 16nm or smaller technologies and strong EE background.

Lead DRAM design verification at Micron in Boise. Drive UVM-based testbenches, AI-powered automation, and coverage closure for next-gen memory. Requires 10+ years, SystemVerilog/UVM expertise, and strong technical leadership.

Lead SSD system design and architecture at Micron in Longmont, CO. Requires 6+ years in SSD development, deep PCIe/NVMe expertise, and strong cross-functional leadership. Shape next-gen storage solutions.

Lead NAND datapath architecture and design at Micron in Tokyo. Requires 8+ years in memory datapath, SRAM or high-speed custom design, timing closure expertise, and daily hands-on AI use to reshape engineering workflows.

Lead GPU server and rack-scale infrastructure design for a fast-growing AI cloud platform in Bellevue, WA. Hybrid Principal role driving NVIDIA/AMD architecture, ODM partnerships, and next-gen AI compute at production scale.

Join Astera Labs as a Principal Physical Design Engineer in Singapore. Lead block and top-level implementation in advanced nodes, drive timing closure, and integrate high-speed IPs. 5-10 years of experience required.

Lead analog and mixed-signal IC design at Astera Labs in Irvine. Requires MS/PhD, 8+ years high-speed CMOS/FinFET experience with PLLs, SerDes, and data converters. Shape next-gen AI connectivity.

Lead architect role for clock generation and distribution in advanced mixed-signal ICs at Analog Devices Ireland. Requires PhD, 5-10 years analog design experience, PLL and SerDes expertise.

FormFactor seeks a Principal PCB Design Engineer in Gyeonggi-Do, Korea. Requires Cadence Allegro expertise, high-speed digital and DDR memory design skills, plus HDI experience. Join a leading semiconductor test technology innovator.

Lead SerDes/PHY IP verification at Astera Labs in San Jose. Requires 8+ years in UVM/SystemVerilog, mixed-signal co-simulation, and high-speed protocols like PCIe or CXL. Architect verification for AI connectivity solutions.

Astera Labs seeks a Principal Electrical Design Engineer in San Jose to architect high-speed board-level hardware for AI infrastructure. Requires 12+ years in PCIe Gen5/6 and 400G/800G Ethernet design with strong signal integrity expertise.

Lead mechanical architecture for engine subsystems at Astro Mechanica in San Francisco. Requires 10+ years of hardware design leadership, expert CAD and GD&T skills, plus mentoring ability. Competitive benefits included.

Principal Analog Design Engineer in Duluth to architect and verify CMOS analog blocks for custom ASICs. Requires 10-15 years of analog design experience and DDR5/DDR6 I/O expertise.

Renesas seeks a Principal Digital Design Engineer in San Jose to lead SOC architecture and RTL development. Requires 8+ years experience, strong protocol knowledge, and offers a dynamic, multicultural environment.

Lead AI/ML innovation in EDA at Renesas as Principal Engineer in Hyderabad or Bangalore. Requires 15+ years in AI/ML, GenAI and Agentic AI, plus Tcl/Perl/Python scripting for RTL-to-GDS flows.

Lead SoC verification at Renesas in Hyderabad as Principal Engineer - Design Verification. Requires 14+ years in SoC verification, UVM, System Verilog, AHB/AXI and memory controllers. Drive next-gen MCU/MPU verification.

Renesas seeks a Principal Digital Design Engineer in San Jose to lead SOC architecture and RTL design. Requires MSEE/PhD with 8+ years experience, strong protocol knowledge, and AI-savvy mindset.

Lead analog and mixed-signal IC design at WD in San Jose. Requires hands-on CMOS expertise (40nm and below), EDA tools proficiency, and a proven record of successful tape-outs and mass production.

Lead HV/EHV cable system design projects at AECOM in Glasgow. Requires technical leadership, National Grid TP and IEC standards expertise, and multidisciplinary team coordination. Shape sustainable infrastructure.

Lead HV/EHV cable system design projects at AECOM in Bristol. Requires technical leadership, National Grid TP and IEC standards expertise, and multidisciplinary team coordination. Shape sustainable infrastructure with a global team.