Digital Engineer Jobs

Senior Site Reliability Engineer with Azure expertise needed for an international Cloud, DevOps and containerization project in Lisbon. Requires AKS, Terraform, Python and Agile skills, plus fluent English. Hybrid work model, 2 days per week in office.

Kepler seeks an FPGA Digital Design Engineer in Toronto to build next-gen satellite payloads. Requires 5+ years RTL experience with Verilog/VHDL, Xilinx Zynq/UltraScale, and strong DSP and scripting skills.

Renesas seeks a Staff Digital Verification Engineer in Bengaluru with 7+ years of UVM/SystemVerilog experience to own verification of complex SoC blocks from planning through coverage closure.

Lead digital design for Power Management ICs at Renesas in Bengaluru. Requires expertise in RTL coding, Verilog/System-Verilog, synthesis, STA, and defining digital/analog boundaries. Join a global semiconductor leader.

Lead digital RTL design role in Austin focused on advanced power management ICs. Requires 10+ years of EE/ECE experience, Verilog, CDC/RDC/LINT clean design, and serial interface expertise. Includes technical mentorship and design automation.

Renesas seeks a Sr. Staff Digital Engineer in Zhubei to drive DFT architecture for complex SoCs. Requires 5+ years in scan, MBIST, boundary scan and low-power DFT, plus RTL and ATPG expertise.

Renesas seeks a Principal Digital Design Engineer in San Jose to lead SOC architecture and RTL design. Requires MSEE/PhD with 8+ years experience, strong protocol knowledge, and AI-savvy mindset.

Continental seeks a Digital Service Engineer in Meerut with a bachelor's in electrical engineering and 5+ years in industrial automation. Drive machine connectivity, IT system integration, and cybersecurity compliance to boost manufacturing efficiency.

Senior MCU and Digital Power Application Engineer role in Taipei requiring 8+ years in embedded systems, C firmware, and digital control theory. Support customers with Renesas MCU and power solutions, DC-DC converters, and system debugging.

Senior Digital Design Engineer role in Zurich combining SoC digital design with ownership of AI-assisted engineering tools. Requires 5+ years in digital IC/SoC design, Verilog/SystemVerilog skills, and proven experience integrating AI into IC design workflows.

Join as an Associate Digital Engineer in Ho Chi Minh. Work with Verilog/SystemVerilog on RTL design, digital sub-systems, and verification. Requires a relevant degree and basic RTL or scripting knowledge.

Renesas seeks a Principal Digital Design Engineer in San Jose to lead SOC architecture and RTL design. Requires 8+ years experience, strong protocol knowledge, and offers a dynamic, multicultural environment.

Lead digital design for advanced power management ICs in Austin. Requires 10+ years EE/ECE experience, Verilog expertise, and strong debug skills. Mentor junior engineers and drive innovative chip development.

Join Continental's Digital Solutions IT team in Lousado as a Data Engineer. Build and maintain cloud-based data pipelines and streaming solutions using Java, SQL, Kafka and Apache Flink in an Agile SCRUM environment.

Renesas seeks a Staff Digital Mixed-Signal Systems Engineer in Austin to develop and verify digital data paths for next-gen power management in AI and datacenter applications. Requires 5+ years experience and strong DSP skills.

Renesas seeks a Senior Staff Digital Engineer in Austin to lead verification of control-loop features for AI and datacenter power products. Requires 8+ years in mixed-signal verification and digital power control.

Renesas seeks a Senior Staff Digital Systems & Emulation Engineer in Austin to build FPGA-based emulation platforms for next-gen power management products. Requires 10+ years in digital design, Verilog/SystemVerilog, and FPGA expertise.

Renesas seeks a Senior Digital Engineer in Austin to verify control-loop features in advanced digital power management products for AI and datacenter applications. Requires 5+ years in mixed-signal verification and digital power control.

Senior digital design role in Catania for an engineer with 8-12 years of experience and EE/ECE degree. Work on advanced power management ICs, leading RTL design, verification and automation with Verilog and SystemVerilog.

Renesas seeks a Sr Staff Digital Engineer in San Jose to define SoC architecture and develop RTL using Verilog/SystemVerilog. Requires MSEE/PhD with 8+ years experience in ASIC/SoC design, timing closure, and protocols like AXI, USB, and SPI.