Digital Engineer Jobs

Lead ASIC digital design at Micron in Minneapolis. Requires 8+ years, strong SystemVerilog RTL skills, and DRAM/memory controller expertise. Shape next-gen memory solutions with competitive pay.

Join CERN's IC Technology R&D team in Geneva as a Systems and Digital ASIC Engineer. Work on advanced electronics for particle detectors, bridging system-level modelling with digital ASIC design using VHDL, Verilog and C++.

Join Analog Devices in Singapore as a Staff Digital IC Design Engineer. Requires MSEE/PhD with 7+ years in RTL design and mixed-signal integration. Shape next-gen semiconductor solutions.

Senior Digital Verification Engineer role in Singapore developing cutting-edge Optical Control ICs for AI data centers. Requires 3+ years SoC verification experience with SystemVerilog, UVM, and AMBA protocols.

Airbus Defence & Space seeks a Digital Data Engineer in Getafe to design and deploy data integration pipelines across business, engineering and machine sources. Requires 5+ years with ETL/ELT platforms, Python and security clearance eligibility.

Senior ASIC Digital Design Engineer role in Hsinchu, Taiwan, verifying configurable system-level IP and subsystems for next-gen RISC-V platforms. Requires a Master's degree and hands-on Verilog/SystemVerilog, C/C++ or Python skills.

Qualinx seeks a Senior Digital Validation Engineer in Delft to validate SoC-level digital systems for low-power GNSS and IoT chips. Requires BSc/MSc, Python, FPGA/Zynq, bus protocols, and lab automation skills. Enjoy equity and wellness benefits.

Join Efficient Computer in San Francisco as a Digital Verification Engineer. Build UVM/SystemVerilog testbenches, drive coverage closure, and debug simulations. Requires 4+ years ASIC/SoC verification experience and Python skills.

Senior Digital Design Engineer role at Analog Devices in the US, developing FPGA-based designs for aerospace and defense applications. Requires high-speed PCB design, RTL skills, and U.S. citizenship with Secret Clearance eligibility.

Join Continental as a Digital/Field Service Engineer in Slough, supporting connected fleet solutions across the UK and Ireland. Requires tyre technology expertise, data analytics skills, and fleet telematics knowledge.

Accenture Federal Services seeks a Digital Engineer in Honolulu to lead enterprise logistics platform integration and digital transformation. Requires 7+ years in systems engineering and expertise in SharePoint and data analytics.

Lead mixed-signal electrical design for cUAS systems at Axon in Sterling. Requires expertise in high-speed digital, FPGA, RF, and EMI/EMC with Altium proficiency. Competitive salary, 401k match, and comprehensive benefits.

Join Anduril as a Digital Tools Engineer in Costa Mesa to lead supply chain system projects end-to-end. Requires 4+ years in ERP/MRP administration and strong project management skills.

Senior Data Engineer needed for a 100% remote role in Panama. Requires 5-7 years of experience with PySpark, Databricks, and ETL pipeline architecture. Enjoy competitive USD pay and flexible remote work.

Join Truelogic as a Senior Data Engineer for Digital Marketing, working fully remote from Brazil. Leverage 5-7 years of PySpark and Databricks expertise to build scalable ETL pipelines with competitive USD pay.

Senior Digital Platform Support Engineer to own Vercel platform operations for enterprise web apps. Requires 5+ years AWS, AEM as Cloud Service expertise, and Next.js/React knowledge. Hybrid role in Chicago, Peoria, Dallas, Broomfield or Cary with full benefits.

Join Avery Dennison as a Digital Solution Engineer in Suzhou. Leverage Python, GenAI/LLMs, and lean automation to optimize shop-floor processes and drive M4.0 deployment. Requires 2+ years in manufacturing operations and a relevant degree.

Lead mixed-signal electrical design for cUAS systems at Axon/Dedrone in Sterling. Requires EE degree, Altium, FPGA, RF and EMI/EMC expertise. Competitive salary, 401k match, paid parental leave.

Kepler Communications seeks an FPGA Digital Design Engineer in Toronto for a 6+ month contract. Requires 5+ years RTL experience with Verilog/SystemVerilog, Xilinx Zynq/UltraScale, and strong timing closure skills.

Renesas seeks a Principal Digital Design Engineer in San Jose to lead SOC architecture and RTL development. Requires 8+ years experience, strong protocol knowledge, and offers a dynamic, multicultural environment.