CrawlJobs Logo

Filters

Location
Salary

Design Verification Engineer Jobs

67 Job Offers

Senior ASIC Design Verification Engineer
Save Icon
Senior ASIC Design Verification Engineer sought for a Bengaluru-based role. Drive advanced verification using UVM and SystemVerilog, owning end-to-end block and full-chip validation. Requires 15+ years of experience, strong UVM expertise, and scripting skills in Perl/Python. Enjoy health benefits...
Location Icon
Location
India , Bengaluru
Salary Icon
Salary
Not provided
https://www.hpe.com/ Logo
Hewlett Packard Enterprise
Expiration Date
Until further notice
Principal Silicon Design Verification Engineer
Save Icon
Principal Silicon Design Verification Engineer sought by Microsoft’s Cloud Hardware team in Santa Clara, CA. Drive functional validation of PCIe IP using UVM/C test benches and VIP. Requires expertise in protocol verification (PCIe Gen6/7) and a degree in Electrical Engineering or related field. ...
Location Icon
Location
United States , Santa Clara
Salary Icon
Salary
142800.00 - 304200.00 USD / Year
https://www.microsoft.com/ Logo
Microsoft Corporation
Expiration Date
Until further notice
Principal Silicon Design Verification Engineer
Save Icon
Principal Silicon Design Verification Engineer at Microsoft in Mountain View, CA. Drive pre-silicon verification strategy for security IP, owning C/C++ and SystemVerilog/UVM test content at SoC level. Requires deep expertise in C/C++, UVM, and Python, with a Doctorate or equivalent experience. Le...
Location Icon
Location
United States , Mountain View
Salary Icon
Salary
142800.00 - 274800.00 USD / Year
https://www.microsoft.com/ Logo
Microsoft Corporation
Expiration Date
Until further notice
Staff Design Verification Engineer
Save Icon
AMD seeks a Staff Design Verification Engineer in Cork, Ireland, to verify next-gen PCIe Controller Sub-Systems for AI, gaming, and PC SOCs. You will lead UVM/SystemVerilog testbench development, low-power verification (UPF), and coverage closure. Requires 7+ years of DV experience, expertise in ...
Location Icon
Location
Ireland , Cork
Salary Icon
Salary
Not provided
amd.com Logo
AMD
Expiration Date
Until further notice
New
ASIC Engineer, Design Verification
Save Icon
Meta seeks a Staff ASIC Design Verification Engineer in Sunnyvale, CA to lead UVM-based verification for custom silicon powering AI/ML, networking, and video processing. You will architect scalable environments, drive end-to-end IP/SoC verification, and collaborate with design teams to ensure fir...
Location Icon
Location
United States , Sunnyvale
Salary Icon
Salary
178000.00 - 250000.00 USD / Year
meta.com Logo
Meta
Expiration Date
Until further notice
Design Verification Engineer
Save Icon
Join AMD in Vancouver, Canada as a Design Verification Engineer to shape next-gen computing. You'll develop UVM testbenches, write SystemVerilog test cases, and analyze coverage for AI and data center products. Ideal candidates hold a Master’s or Bachelor’s in electrical/computer engineering with...
Location Icon
Location
Canada , Vancouver
Salary Icon
Salary
105600.00 - 158400.00 CAD / Year
amd.com Logo
AMD
Expiration Date
Until further notice
Sr ASIC Design Verification Engineer (NetSec)
Save Icon
Join a top-tier ASIC team in Santa Clara as a Sr Design Verification Engineer, driving next-gen firewall ASICs from concept to mass production. Leverage SystemVerilog and UVM to architect test benches, define coverage, and debug across simulation, emulation, and formal verification. Ideal candida...
Location Icon
Location
United States , Santa Clara
Salary Icon
Salary
Not provided
paloaltonetworks.com Logo
Palo Alto Networks
Expiration Date
Until further notice
Design Verification Engineer - Machine Learning Accelerators
Save Icon
Join Meta's Reality Labs as a Design Verification Engineer in Sunnyvale, CA, driving cutting-edge Machine Learning Accelerators for AR and smart devices. Leverage 10+ years of SystemVerilog/UVM and C/C++ expertise to lead IP and SoC verification, ensuring first-pass silicon success. Collaborate o...
Location Icon
Location
United States , Sunnyvale
Salary Icon
Salary
178000.00 - 250000.00 USD / Year
meta.com Logo
Meta
Expiration Date
Until further notice
Principal Silicon Design Verification Engineer
Save Icon
Principal Silicon Design Verification Engineer sought to validate cutting-edge DPU silicon in Santa Clara. You will lead pre-silicon SoC verification using UVM/C, develop test plans, and debug complex designs for datacenter solutions. Requires a Doctorate or Master’s in EE/CE with 3-6+ years of e...
Location Icon
Location
United States , Santa Clara
Salary Icon
Salary
142800.00 - 304200.00 USD / Year
https://www.microsoft.com/ Logo
Microsoft Corporation
Expiration Date
Until further notice
Senior Design Verification Engineer – Security IP
Save Icon
Senior Design Verification Engineer – Security IP at AMD in Bangalore. Join a culture of innovation to verify next-gen security architectures. Requires 5+ years experience, SystemVerilog, UVM, and scripting skills. Develop block/MP subsystem testbenches, debug simulations, and drive verification ...
Location Icon
Location
India , Bangalore
Salary Icon
Salary
Not provided
amd.com Logo
AMD
Expiration Date
Until further notice
Design Verification Engineer
Save Icon
AMD in Markham, Canada seeks a Design Verification Engineer to plan, build, and execute verification for graphics processor IP. You will develop UVM-based frameworks, debug RTL/firmware, and drive coverage closure using SystemVerilog, C++, and Perl/Python. Ideal candidates hold a Bachelors/Master...
Location Icon
Location
Canada , Markham
Salary Icon
Salary
128000.00 - 192000.00 CAD / Year
amd.com Logo
AMD
Expiration Date
Until further notice
ASIC Design Verification Engineer
Save Icon
Join Cisco’s Common Hardware Group in Bangalore as an ASIC Design Verification Engineer. Leverage 7+ years of UVM/SystemVerilog expertise to architect and build top-level DV environments for cutting-edge Silicon One ASICs. Drive verification from test plans to gate-level simulations, collaboratin...
Location Icon
Location
India , Bangalore
Salary Icon
Salary
Not provided
Cisco
Expiration Date
Until further notice
Senior Design Verification Engineer
Save Icon
Senior Design Verification Engineer at Microsoft Silicon in Mountain View, CA. Drive pre-silicon functional verification for cloud infrastructure powering Azure, Bing, and Office 365. Requires expertise in Verilog, C/C++, Python, and developing complex test environments. Join a world-class team d...
Location Icon
Location
United States , Mountain View
Salary Icon
Salary
119800.00 - 261000.00 USD / Year
https://www.microsoft.com/ Logo
Microsoft Corporation
Expiration Date
Until further notice
Design Verification Engineer
Save Icon
Join AMD as a Design Verification Engineer in Ottawa, Canada, and shape the future of AI and computing. You’ll develop UVM-based testbenches, debug Verilog RTL, and deploy advanced verification methodologies. Proficiency in System Verilog, Python, and ASIC design is essential. Be part of an innov...
Location Icon
Location
Canada , Ottawa
Salary Icon
Salary
128000.00 - 192000.00 CAD / Year
amd.com Logo
AMD
Expiration Date
Until further notice
Asic/Fpga Design Verification Engineer
Save Icon
Teradyne seeks an ASIC/FPGA Design Verification Engineer in North Reading, MA. You will develop testbench architectures and UVM environments using System Verilog. Requires 3+ years of experience with digital logic verification, Cadence Xcelium, and protocols like SPI/AXI. Enjoy medical, dental, v...
Location Icon
Location
United States , North Reading
Salary Icon
Salary
98700.00 - 157900.00 USD / Year
teradyne.com Logo
Teradyne
Expiration Date
Until further notice
Asic/fpga Design Verification Engineer
Save Icon
Join a leading Logic Design Engineering team in North Reading, US as an ASIC/FPGA Design Verification Engineer. Leverage 5+ years of expertise in System Verilog, UVM, and Cadence Xcelium to develop robust testbench architectures and close functional coverage. Collaborate with cross-functional tea...
Location Icon
Location
United States , North Reading
Salary Icon
Salary
123100.00 - 196900.00 USD / Year
teradyne.com Logo
Teradyne
Expiration Date
Until further notice
Senior Design Verification Engineer – Graphics & Multimedia IP
Save Icon
Senior Design Verification Engineer needed in Hyderabad, India to lead verification of AMD’s graphics and multimedia IP. You will build UVM-based testbenches, debug RTL and firmware, and collaborate with architects to ensure bug-free designs. Requires expertise in SystemVerilog, C++, UVM, and gra...
Location Icon
Location
India , Hyderabad
Salary Icon
Salary
Not provided
amd.com Logo
AMD
Expiration Date
Until further notice
Principal Quantum Design Verification Engineer
Save Icon
Join Microsoft Quantum in Redmond as a Principal Quantum Design Verification Engineer to drive scalable, fault-tolerant quantum computing. You will own verification environments for complex SoC and IP designs, leveraging UVM, SystemVerilog, and AMS models. Requires a Doctorate or equivalent exper...
Location Icon
Location
United States , Redmond
Salary Icon
Salary
139900.00 - 274800.00 USD / Year
https://www.microsoft.com/ Logo
Microsoft Corporation
Expiration Date
Until further notice
Senior Quantum Design Verification Engineer
Save Icon
Senior Quantum Design Verification Engineer sought by Microsoft in Redmond, WA. Drive pre-silicon simulation and post-silicon validation for cutting-edge quantum SoCs. Requires a Doctorate/Master’s/Bachelor’s in Physics or Engineering with industry experience. Own verification environments, test ...
Location Icon
Location
United States , Redmond
Salary Icon
Salary
119800.00 - 234700.00 USD / Year
https://www.microsoft.com/ Logo
Microsoft Corporation
Expiration Date
Until further notice
ASIC Design Verification Engineer
Save Icon
Senior ASIC Design Verification Engineer sought by Cisco’s Common Hardware Group in Bangalore. Leverage 7+ years of UVM/System Verilog expertise to architect and build top-level DV environments for cutting-edge Cisco Silicon One ASICs. Drive verification from test bench creation to post-silicon b...
Location Icon
Location
India , Bangalore
Salary Icon
Salary
Not provided
duo.com Logo
Duo Security
Expiration Date
Until further notice
Previous 1 2 3 4 Next

About the Design Verification Engineer role

Design Verification Engineer jobs represent a critical pillar in the semiconductor and hardware development industry, ensuring that complex integrated circuits and systems-on-chip (SoCs) function correctly before they are manufactured. Professionals in this role act as the quality gatekeepers of the digital design world, tasked with the rigorous process of confirming that a design meets its specified requirements and operates without critical bugs. The primary responsibility of a Design Verification Engineer is to create and execute comprehensive verification plans. This involves developing sophisticated testbenches using industry-standard methodologies like Universal Verification Methodology (UVM) and languages such as SystemVerilog, Verilog, and C++.

They write both directed and constrained-random tests to stress-test the design, simulating millions of possible scenarios to uncover hidden flaws. A significant part of the daily work involves debugging test failures, working closely with RTL designers to identify whether a bug lies in the design itself or in the test environment. They use advanced simulation tools to analyze waveforms and trace logic errors, ensuring that every functional corner case is covered. Coverage analysis is another core duty; engineers must track code coverage and functional coverage metrics to guarantee that no part of the design remains untested.

This often requires modifying tests or adding new ones to meet strict coverage goals. Beyond pre-silicon simulation, many Design Verification Engineer jobs involve post-silicon validation, where they help bring up actual silicon in the lab, running tests on real hardware to ensure it matches simulation results. They also work with emulation platforms to run software workloads at higher speeds, bridging the gap between simulation and final production. Collaboration is essential, as these engineers interface daily with architects, design engineers, firmware teams, and design-for-test (DFT) specialists to align verification strategies and resolve issues early in the development cycle.

Typical skills required for these roles include deep proficiency in SystemVerilog and UVM, strong debugging abilities, and experience with scripting languages like Perl, Python, or Makefile for automation. A solid understanding of digital logic design, computer architecture, and protocols is also crucial. Most positions require a Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field, coupled with several years of hands-on verification experience. As chips grow more complex—integrating AI accelerators, advanced graphics, and high-speed interfaces—the demand for meticulous and innovative Design Verification Engineer jobs continues to rise, making this profession indispensable for delivering reliable, high-performance silicon to market.