Jobs in Chandler, United States

Lead verification strategy for next-gen DDR6 semiconductor memory interfaces in Chandler. Requires deep SystemVerilog and UVM expertise, technical ownership of complex verification efforts, and strong collaboration with RTL design teams.

Renesas seeks a Staff Verification Engineer in Chandler to verify mixed-signal automotive PMIC designs. Requires 12+ years of experience, RNM/AMS modeling, GLS flows, and ISO 26262 expertise.

Lead the architectural evolution of PMIC and mixed-signal products as a global technical authority in Chandler. Requires 12+ years in power management, CMOS expertise, and proven technical leadership on complex ICs.

Lead mixed-signal verification for PMICs, chargers and switching regulators in Chandler. Requires 8-12+ years with AMS/DMS, SystemVerilog, UVM, Verilog-AMS and Cadence tools. Drive chip-level sign-off and behavioral modeling.