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Jobs in Chandler, United States

31 job offers

Senior Staff Device Characterization Engineer
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Lead power device characterization projects in Chandler as a Senior Staff Engineer. Requires 10+ years in semiconductor testing, lab equipment expertise, and Python or MATLAB skills. Apply now.
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Operating Engineer
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JLL seeks an Operating Engineer in Chandler, AZ to maintain and repair critical facility systems. Requires expertise in electrical, HVAC, or plumbing plus strong troubleshooting skills. Enjoy 401(k) matching, full medical benefits, and paid parental leave.
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Principal ESD Engineer
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Renesas seeks a Principal ESD Engineer in Chandler to lead ESD methodology, custom IP development, and sign-off verification for FinFET SoCs and SerDes. Requires 10+ years of ESD design expertise and strong leadership skills.
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Copy of Senior Staff Analog Engineer
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Senior Staff Analog Engineer in Chandler to lead PMIC and mixed-signal architecture across the full lifecycle. Requires 8-10 years in power management, CMOS expertise, and proven technical leadership with strong mentoring skills.
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Senior Staff Analog Engineer
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Lead analog design for complex power management ICs in Chandler. Guide a team, drive innovation, and represent Dialog to customers. Requires 5-10+ years analog design experience and a B.S./M.S. in EE or related field.
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Senior Staff Analog Engineer
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Lead analog design for complex power management ICs in Chandler. Guide team members on best practices, drive improvements, and represent the company to external customers. Requires 5-10+ years analog design experience and B.S./M.S. in EE.
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Principal Design Verification Engineer
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Lead verification strategy for next-gen DDR6 semiconductor memory interfaces in Chandler. Requires deep SystemVerilog and UVM expertise, technical ownership of complex verification efforts, and strong collaboration with RTL design teams.
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Principal Analog Design Engineer
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Lead the architectural evolution of PMIC and mixed-signal products as a global technical authority in Chandler. Requires 12+ years in power management, CMOS expertise, and proven technical leadership on complex ICs.
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Staff Mixed Signal Verification Engineer
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Lead mixed-signal verification for PMICs, chargers and switching regulators in Chandler. Requires 8-12+ years with AMS/DMS, SystemVerilog, UVM, Verilog-AMS and Cadence tools. Drive chip-level sign-off and behavioral modeling.
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Senior Staff Semiconductor Test Engineer PMIC
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Senior Staff Semiconductor Test Engineer PMIC
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Principal Analog Design Engineer
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Senior Staff Analog Design Engineer
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Principal Electrical Engineer
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Staff Mixed Signal Verification Engineer
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Senior Staff Analog Engineer
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Senior Staff Semiconductor Test Engineer PMIC
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Senior Staff Semiconductor Test Engineer PMIC
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Senior Staff Analog Engineer
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Senior Staff Analog Design Engineer
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