Renesas Electronics - United States, Hybrid work

Lead verification strategy for next-gen DDR6 semiconductor memory interfaces in Plano. Requires deep SystemVerilog and UVM expertise, technical ownership of complex verification efforts, and strong collaboration with RTL design teams.

Renesas seeks a Staff Package Design Engineer in Tempe, AZ to design advanced packages (FCBGA, SiP, WLCSP, power modules). Requires 4+ years CAD layout experience and strong OSAT/substrate collaboration skills.

Renesas seeks an AI Search & SEO Specialist in Austin to optimize content visibility across AI answer engines and organic search. Requires 3+ years SEO experience and tools like GSC, Ahrefs, and SEMrush.

Lead verification strategy for next-gen DDR6 semiconductor memory interfaces in Austin. Requires deep SystemVerilog and UVM expertise, technical ownership of complex verification efforts, and collaboration with RTL teams. DDR experience a plus.

Senior Staff Applications Engineer in Austin to design multiphase DC/DC power solutions for AI and cloud infrastructure. Requires 10+ years in power design, high-speed interfaces, and lab validation with strong cross-functional leadership.

Lead verification strategy for next-gen DDR6 semiconductor memory interfaces in Duluth. Requires deep SystemVerilog and UVM expertise, technical ownership of complex verification efforts, and collaboration with RTL design teams. DDR experience a plus.

Lead verification strategy for next-gen DDR6 semiconductor memory interfaces in Chandler. Requires deep SystemVerilog and UVM expertise, technical ownership of complex verification efforts, and strong collaboration with RTL design teams.

Renesas seeks a Staff Verification Engineer in Chandler to verify mixed-signal automotive PMIC designs. Requires 12+ years of experience, RNM/AMS modeling, GLS flows, and ISO 26262 expertise.

Lead verification strategy for next-gen DDR6 memory interface products in San Jose. Requires deep SystemVerilog and UVM expertise, technical ownership of complex semiconductor verification, and close collaboration with RTL teams.

Lead advanced semiconductor packaging development at Renesas in San Jose. Requires MSc/PhD, 5+ years packaging experience, and expertise in WLP, 2.5D/3D, SiP, and flip-chip technologies.

Lead the architectural evolution of PMIC and mixed-signal products as a global technical authority in Chandler. Requires 12+ years in power management, CMOS expertise, and proven technical leadership on complex ICs.

Lead digital design projects for advanced power management ICs in Austin. Requires 10+ years EE/ECE experience, Verilog expertise, and strong leadership skills. Mentor junior engineers and drive innovation.