Renesas Electronics - United States, Hybrid work

Join Renesas as a Field Applications Engineer in Austin, supporting AI and datacenter power solutions. Recent EE graduates gain hands-on experience in power electronics, DC-DC converters, and customer-facing engineering.

Lead product development for AI-focused power solutions at Renesas in San Jose. Requires 10+ years in semiconductor product management, NPI expertise, and cross-functional leadership. Drive volume ramps and customer programs.

Senior Analog Engineer needed in San Jose to design and verify high-performance analog and mixed-signal ICs for automotive, industrial, and power management applications. Requires strong CMOS and Cadence Virtuoso expertise.

Senior Product Support Engineer role in La Jolla Ranch requiring 6+ years of PCB design and EDA support experience. Advanced Altium expertise, root cause analysis, and strong English communication skills needed.

Renesas seeks a Principal Digital Design Engineer in San Jose to lead SOC architecture and RTL design. Requires 8+ years experience, strong protocol knowledge, and offers a dynamic, multicultural environment.

Lead digital design for advanced power management ICs in Austin. Requires 10+ years EE/ECE experience, Verilog expertise, and strong debug skills. Mentor junior engineers and drive innovative chip development.

Renesas seeks a Staff Digital Mixed-Signal Systems Engineer in Austin to develop and verify digital data paths for next-gen power management in AI and datacenter applications. Requires 5+ years experience and strong DSP skills.

Lead package technology development for AI and data center power products at Renesas in Tempe. Requires 12-15 years of semiconductor packaging experience and expertise in SiP, wafer-level, and flip-chip packaging.

Experienced Staff Mask Design Engineer needed in Chandler to lead analog and mixed-signal IC layout for automotive applications. Requires 8+ years of layout experience, advanced CMOS BCD expertise, and strong physical verification skills.

Join Renesas as a Design Verification Intern in Duluth, GA (hybrid) for Summer 2027. Work on cutting-edge DDR5/DDR6 memory buffer chips using Verilog, SystemVerilog and UVM. Enrolled students only.

Join Renesas in Austin as a Senior Power Management Applications Engineer. Drive adoption of DC-DC and multiphase power solutions, support tier-1 customer designs, and define next-gen power ICs. Hands-on DC/DC conversion expertise required.

Lead verification strategy for next-gen DDR6 semiconductor memory interfaces in Plano. Requires deep SystemVerilog and UVM expertise, technical ownership of complex verification efforts, and strong collaboration with RTL design teams.