Principal Design Engineer Jobs (Hybrid work)

AECOM seeks a Principal Design Engineer in Dubai to lead complex water and wastewater projects. Requires 15+ years in wet utilities, 8+ in GCC, PE/Peng certification, and expertise in hydraulic modeling and municipal infrastructure.

Taara (Google's Moonshot Factory) seeks a Principal Analog/Mixed-Signal ASIC Design Engineer in Sunnyvale to develop next-gen photonic modules. Requires PhD, 10+ years experience, and BCD tapeout expertise.

Lead GPU server and rack-scale infrastructure design for a fast-growing AI cloud platform in Bellevue, WA. Hybrid Principal role driving NVIDIA/AMD architecture, ODM partnerships, and next-gen AI compute at production scale.

Principal Analog Design Engineer in Duluth to architect and verify CMOS analog blocks for custom ASICs. Requires 10-15 years of analog design experience and DDR5/DDR6 I/O expertise.

Renesas seeks a Principal Digital Design Engineer in San Jose to lead SOC architecture and RTL development. Requires 8+ years experience, strong protocol knowledge, and offers a dynamic, multicultural environment.

Renesas seeks a Principal Digital Design Engineer in San Jose to lead SOC architecture and RTL design. Requires MSEE/PhD with 8+ years experience, strong protocol knowledge, and AI-savvy mindset.

Lead HV/EHV cable system design projects at AECOM in Glasgow. Requires technical leadership, National Grid TP and IEC standards expertise, and multidisciplinary team coordination. Shape sustainable infrastructure.

Lead HV/EHV cable system design projects at AECOM in Bristol. Requires technical leadership, National Grid TP and IEC standards expertise, and multidisciplinary team coordination. Shape sustainable infrastructure with a global team.

Lead HV/EHV cable system design projects at AECOM in Leeds. Requires technical leadership, National Grid TP and IEC standards expertise, and multidisciplinary team coordination. Shape sustainable infrastructure with a global team.

AECOM seeks a Principal Cable System Design Engineer in Newcastle-Upon-Tyne to lead HV/EHV cable projects from concept to completion. Requires technical leadership, National Grid standards expertise, and multidisciplinary team coordination skills.

Renesas seeks a Principal Digital Design Engineer in San Jose to lead SOC architecture and RTL design. Requires 8+ years experience, strong protocol knowledge, and offers a dynamic, multicultural environment.

Lead digital design for advanced power management ICs in Austin. Requires 10+ years EE/ECE experience, Verilog expertise, and strong debug skills. Mentor junior engineers and drive innovative chip development.

Lead verification strategy for next-gen DDR6 semiconductor memory interfaces in Plano. Requires deep SystemVerilog and UVM expertise, technical ownership of complex verification efforts, and strong collaboration with RTL design teams.