Principal Design Engineer United States Jobs

Taara (Google's Moonshot Factory) seeks a Principal Analog/Mixed-Signal ASIC Design Engineer in Sunnyvale to develop next-gen photonic modules. Requires PhD, 10+ years experience, and BCD tapeout expertise.

Lead silicon photonic IC design at Voyant Photonics in NYC, driving chip-scale LiDAR and optical circuit switches for AI data centers. Requires PhD, 7+ years PIC design experience, and full tapeout ownership.

Lead the end-to-end architecture of a custom AMS ASIC for an implantable neural interface in Alameda, CA. Requires 10+ years of AMS IC design, multiple tapeouts, and low-noise ultra-low-power expertise.

Lead DRAM design verification at Micron in Boise. Drive UVM-based testbenches, AI-powered automation, and coverage closure for next-gen memory. Requires 10+ years, SystemVerilog/UVM expertise, and strong technical leadership.

Lead SSD system design and architecture at Micron in Longmont, CO. Requires 6+ years in SSD development, deep PCIe/NVMe expertise, and strong cross-functional leadership. Shape next-gen storage solutions.

Lead GPU server and rack-scale infrastructure design for a fast-growing AI cloud platform in Bellevue, WA. Hybrid Principal role driving NVIDIA/AMD architecture, ODM partnerships, and next-gen AI compute at production scale.

Lead analog and mixed-signal IC design at Astera Labs in Irvine. Requires MS/PhD, 8+ years high-speed CMOS/FinFET experience with PLLs, SerDes, and data converters. Shape next-gen AI connectivity.

Lead SerDes/PHY IP verification at Astera Labs in San Jose. Requires 8+ years in UVM/SystemVerilog, mixed-signal co-simulation, and high-speed protocols like PCIe or CXL. Architect verification for AI connectivity solutions.

Astera Labs seeks a Principal Electrical Design Engineer in San Jose to architect high-speed board-level hardware for AI infrastructure. Requires 12+ years in PCIe Gen5/6 and 400G/800G Ethernet design with strong signal integrity expertise.

Lead mechanical architecture for engine subsystems at Astro Mechanica in San Francisco. Requires 10+ years of hardware design leadership, expert CAD and GD&T skills, plus mentoring ability. Competitive benefits included.

Principal Analog Design Engineer in Duluth to architect and verify CMOS analog blocks for custom ASICs. Requires 10-15 years of analog design experience and DDR5/DDR6 I/O expertise.

Renesas seeks a Principal Digital Design Engineer in San Jose to lead SOC architecture and RTL development. Requires 8+ years experience, strong protocol knowledge, and offers a dynamic, multicultural environment.

Renesas seeks a Principal Digital Design Engineer in San Jose to lead SOC architecture and RTL design. Requires MSEE/PhD with 8+ years experience, strong protocol knowledge, and AI-savvy mindset.

Lead analog and mixed-signal IC design at WD in San Jose. Requires hands-on CMOS expertise (40nm and below), EDA tools proficiency, and a proven record of successful tape-outs and mass production.

Renesas seeks a Principal Digital Design Engineer in San Jose to lead SOC architecture and RTL design. Requires 8+ years experience, strong protocol knowledge, and offers a dynamic, multicultural environment.

Lead digital design for advanced power management ICs in Austin. Requires 10+ years EE/ECE experience, Verilog expertise, and strong debug skills. Mentor junior engineers and drive innovative chip development.

Lead verification strategy for next-gen DDR6 semiconductor memory interfaces in Plano. Requires deep SystemVerilog and UVM expertise, technical ownership of complex verification efforts, and strong collaboration with RTL design teams.