Lead Design Engineer Jobs

Lead RTL design for complex SoCs at Astera Labs in San Jose. Requires 5+ years in SoC/silicon for server, storage or networking, plus timing closure and DFT skills. Scripting automation and RISC-V/Arm a plus.

Lead Physical Design Engineer role at Astera Labs in Singapore. Requires 5+ years in physical design, advanced nodes, Synopsys ICC2/Cadence Innovus, and high-speed IP integration for AI infrastructure.

Lead IBM i (AS/400) Infrastructure Design Engineer role in Hyderabad. Requires deep IBM Power Systems, LPAR, VIOS and HMC expertise plus HA/DR architecture skills. Own platform design and L3 escalations for mission-critical environments.