Renesas Electronics - United States, San Jose, Hybrid work

Renesas seeks a Principal Digital Design Engineer in San Jose to lead SOC architecture and RTL development. Requires 8+ years experience, strong protocol knowledge, and offers a dynamic, multicultural environment.

Lead IC reliability and quality from development to production in San Jose. Requires MS/PhD in EE, Physics or Materials Science, 8+ years in semiconductor reliability, and expertise in JEDEC and AEC-Q100 standards.

Experienced HR Project Manager needed in San Jose to drive key HR initiatives across Renesas. Requires 5-10+ years in consulting, PMO, or HR project management with strong stakeholder coordination skills.

Renesas seeks a Principal Digital Design Engineer in San Jose to lead SOC architecture and RTL design. Requires MSEE/PhD with 8+ years experience, strong protocol knowledge, and AI-savvy mindset.

Lead global product marketing for Renesas memory interface solutions targeting the AI datacenter market in San Jose. Requires 8+ years in business development or technical sales with strong memory market expertise. Drive design wins and shape product roadmaps.

Lead product development for AI-focused power solutions at Renesas in San Jose. Requires 10+ years in semiconductor product management, NPI expertise, and cross-functional leadership. Drive volume ramps and customer programs.

Senior Analog Engineer needed in San Jose to design and verify high-performance analog and mixed-signal ICs for automotive, industrial, and power management applications. Requires strong CMOS and Cadence Virtuoso expertise.

Renesas seeks a Principal Digital Design Engineer in San Jose to lead SOC architecture and RTL design. Requires 8+ years experience, strong protocol knowledge, and offers a dynamic, multicultural environment.

Lead verification strategy for next-gen DDR6 memory interface products in San Jose. Requires deep SystemVerilog and UVM expertise, technical ownership of complex semiconductor verification, and close collaboration with RTL teams.

Lead advanced semiconductor packaging development at Renesas in San Jose. Requires MSc/PhD, 5+ years packaging experience, and expertise in WLP, 2.5D/3D, SiP, and flip-chip technologies.

Lead analog and mixed-signal IC development at Renesas in San Jose. Requires MSEE, 15+ years in precision analog and power management design, plus strong leadership and mentoring skills.