Renesas Electronics - India, On-site work

Lead end-to-end silicon validation strategy for automotive and HPC SoCs at Renesas in Hyderabad. Requires 10-16 years in semiconductor validation, strong Python/C++ automation skills, and proven SoC program delivery from first silicon to production.

Lead software engineering at Renesas in Bengaluru. Requires 12+ years experience, 2+ years managing teams, Java/Kotlin and Python skills, plus GenAI expertise. Mentor engineers and drive innovation in semiconductor tech.

Renesas seeks a Senior Principal Engineer, Silicon Photonics Architect in Hyderabad. Requires 15+ years in silicon photonics, PIC/EIC architecture, and optical transceiver programs. Lead cutting-edge integrated photonics innovation.

Lead AI/ML application development at Renesas in Bengaluru. Requires 10+ years in software engineering, Python, LLMs, RAG, vector databases, Azure Databricks, and React.js. Build scalable AI platforms and data pipelines.

Lead SoC DFT architecture and test strategy at Renesas in Hyderabad. Requires 15+ years of hands-on DFT experience with Scan, ATPG, MBIST, and JTAG across multiple SoC tape-outs.

Renesas seeks a Sr. AI Engineer in Bangalore to build agentic AI systems, RAG pipelines, and production ML solutions. Requires 5+ years in ML, strong Python, and MLOps expertise.

Lead SoC validation strategy for automotive and HPC chips at Renesas in Hyderabad. Requires 18+ years in semiconductor validation, 3+ years in senior technical leadership, and expertise in post-silicon debug and automation-first frameworks.

Renesas seeks a Staff Engineer for STA in Bengaluru to drive full-chip and block-level timing closure. Requires 4-12 years of STA experience, strong SDC and PrimeTime/Tempus skills, plus Tcl, Perl, or Python scripting.

Renesas seeks a Sr Staff Hardware Engineer in Hyderabad to build SystemC/TLM virtual prototypes of SoC, CPU and IP blocks. Requires 10+ years of hardware experience, strong C/C++/SystemC skills and VP tool expertise.

Renesas seeks a Sr. Staff Engineer in Bengaluru with 10+ years of physical design experience. Drive RTL-to-GDSII, PPA optimization, and timing closure using Fusion Compiler, Innovus, and Primetime.

Renesas seeks a Sr Staff Engineer in Bengaluru to architect and deliver high-performance analog/mixed-signal IPs. Requires 10+ years of IC design experience and full lifecycle ownership from specification to silicon validation.

Renesas seeks a Staff/Principal Analog Design Engineer in Bengaluru to architect complex power-management ICs, PMICs, and mixed-signal blocks. Requires 6-15 years of analog design expertise with hands-on PMIC and converter experience.