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Hewlett Packard Enterprise is seeking a VLSI Design Verification Manager to lead design verification for Slingshot™ networking ASICs, the high-performance interconnect used in HPE's flagship HPC and AI supercomputers. HPE Slingshot is a modern, Ethernet-based interconnect purpose-built for large-scale HPC and AI clusters, delivering industry-leading bandwidth, low latency, adaptive routing and scalability for demanding workloads. In this role, you will lead a team of design verification engineers responsible for ensuring functional correctness and quality of complex networking ASICs used in NIC and switch products. You will own verification methodology, execution quality, and sign-off readiness, while growing and mentoring engineers across a range of experience levels. This role manages a team of approximately 8-15 engineers (TCP01–TCP05) and sits at the intersection of deep technical leadership, people development, and program execution.
Job Responsibility
Provide leadership and direction for a team responsible for all phases of pre-silicon design verification, including verification planning, testbench development, coverage closure, regression management, and sign-off reviews
Define, own, and evolve design verification methodology, ensuring consistent, high-quality verification practices across block, subsystem, and full-chip scopes
Ensure development of robust SystemVerilog/UVM-based environments, including stimulus, scoreboards, checkers, assertions, and functional coverage
Drive regression health, failure triage, root-cause isolation, and closure of design issues in close collaboration with logic design and architecture teams
Manage project deliverables, schedules, and staffing to meet program milestones and quality goals
Recruit, mentor, and develop engineers
set performance expectations and support career growth across junior through senior levels
Identify and drive opportunities for process improvement, reuse, automation, and efficiency in verification workflows
Communicate verification status, risks, and readiness clearly to management and cross-functional partners
Requirements
Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent
Typically 10+ years of experience in VLSI design verification, with strong hands-on background in pre-silicon DV
Strong understanding of SystemVerilog and UVM-based verification methodologies
Demonstrated technical leadership in design verification
Ability to lead engineers through influence, technical credibility, mentorship, and clear communication
Experience with verification planning, coverage-driven verification, regression management, and sign-off readiness
Proficiency with DV workflows using industry EDA simulation tools
Strong analytical and problem-solving skills
Excellent written and verbal communication skills
Ability to operate effectively in a multi-site, cross-functional engineering environment
Nice to have
Previous people-management experience, including hiring, coaching, and performance management
Direct experience with Synopsys VCS large-scale regression execution, triage workflows, and performance/throughput optimization
Familiarity with GitHub Enterprise Cloud development workflows and AI tools is a plus
Familiarity with high-performance networking, Ethernet, SERDES, PCIe, or HPC/AI systems is a plus
Experience improving verification efficiency through automation, reuse, or methodology refinement