Verification Engineer Job at Codasip GmbH (Bristol)

Verification Engineer

At Codasip, we’re redefining the future of computing. Following a bold strategic...

Location

France , Villeneuve-Loubet

Salary:

Not provided

Codasip GmbH

Expiration Date

Until further notice

Requirements

Commercial experience with functional processor verification methodologies as applied to CPU or other ASIC verification (simulators, test generation, coverage collection, gate-level simulation, etc.)
Knowledge of verifying CPU architectures or other IP
Fluency and the ability to write clear and concise code in languages like SystemVerilog, Python, C++, Rust, or Go
Past verification ownership of a design block
User knowledge of Linux to enable automation of common tasks
Knowledge of versioning tools (Git, SVN)
Knowledge of RISC-V Architecture
Good knowledge of computer systems and architecture
Analytical thinking and team collaboration skills
Ability to work effectively across teams to debug issues and find root causes

Job Responsibility

Verify RISC-V processors and extensions
Develop verification solutions (e.g., test benches and test bench components, stimulus generation, formal environments)
Collaborate with other engineers in a team responsible for the delivery of all verification activities related to a component or subsystem from start to finish
Define verification strategies for blocks and sub-systems, identifying and utilising the right tools
Review technical specifications, providing feedback from a verification perspective
Run simulations, hunt bugs and complete root cause analysis of complex issues
Define, estimate, prioritise and track your own work
Track and report verification metrics
Craft automated verification flows

Fulltime

Verification Engineer

Teradyne Nextest FPGA Team is looking for experienced verification engineer with...

Location

Costa Rica , Alajuela

Salary:

Not provided

Teradyne

Expiration Date

Until further notice

Requirements

BS in Computer Science, Computer Engineering or Electrical Engineering or related field
English proficiency
8 years of experience with: Digital Design functional verification
Industry standard protocols (e.g. PCIE, AXI)
EDA Tools (e.g. Cadence Xcelium, Simvision)
System Verilog
UVM (Testbench components, development)
Verification IP integration

Job Responsibility

Understand the design requirements from verification perspective
Functional verification using System Verilog and UVM methodology
Create testbench, verification components, and tests
Create self-checking verification environment with data checkers and assertions
Debug failures using waveforms and test log reports
Drive verification completion with 100% functional coverage and code coverage
Interacting with FPGA design, software and hardware team for test strategies and debugging failures

What we offer

Teradyne offers a variety of robust health and well-being benefit programs, including medical, dental, vision, life and health insurance, paid vacation & holidays, tuition assistance programs, and more

Verification Engineer

We are seeking skilled SoC (System-on-Chip) ARM Power architecture, Soc clock an...

Location

India , Noida

Salary:

Not provided

ARM

Expiration Date

Until further notice

Requirements

3 - 6 years of proven experience in working on SoC verification environments across Power verification involving multiple power islands and clock and reset verification
Knowledge of assembly language (preferably ARM), C/C++ and hardware verification languages (e.g. SystemVerilog), shell programming/scripting (e.g. Tcl, Perl, Python etc.)
Experience in one or more of various verification methodologies – UVM/OVM, formal, low power
Good knowledge and working verification experience in Arm M class CPU Processors
Good experience in handling Power aware verification with complex power architecture
Exposure to all stages of verification: requirements collection, creation of test plans, testbench implementation, test cases development, documentation and support
Understanding of the fundamentals of Arm system architectures
Experience with various front-end verification tools - Dynamic simulation tools, Static Simulation tools, UPF, and Debuggers
Experience in working and debugging Soc in DFT mode
Exposure to various front-end verification tools - Questa, VCS, Jasper Gold, Verdi

Job Responsibility

Writing test plans, defining test methodologies, and completing functional verification to the required quality levels and schedules
Leading a team of engineers to own and power, clk/rst verification for a complex IoT chip
Collaborate with engineers in architecture, design, verification, implementation, modeling, performance analysis, silicon validation, FPGA and board development and build a functional verification strategy
Support mentor junior team members

What we offer

Health and Wellness
Work and Life Success
Financial Rewards
Development and Support

Lead Soc Verification Engineer

The focus of this role is to plan, build, and execute the verification of new an...

Location

India , Hyderabad

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

Strong Familiarity with Verification Methodologies such as OVM, UVM, or VMM
Familiarity with Verilog and General Logic Design concepts
Knowledge of system-level architecture including buses like AXI/AHB, bridges, memory controllers such as DDR4/DDR5, and peripherals such as USB, PCIe and Ethernet
Knowledge of industry‑standard cryptographic and security algorithms (e.g., AES, RSA, SHA)
Strong working knowledge of UNIX environment and scripting languages such as Perl or Python
Excellent waveform debug skills using front end industry standard design tools like VCS, NCSIM/XCELIUM, Verdi, QUESTASIM
Experience using UNIX Revision Control tools - ICM manage, CVS, Perforce and bug tracking tools such as JIRA
Experience in verifying multimillion gate chip designs from specifications to tape-out
Excellent communication and presentation skills
Demonstrate the ability to work with cross-functional teams

Job Responsibility

Develop/Maintain tests for functional verification at SOC level
Build testbench components to support the next generation IP
Maintain or improve current verification libraries to support SOC/Full-chip level verification
Provide technical support to other teams
Help Hardware emulation team to port the RTL to Palladium/Zebu or HAPS/Protium platforms.

Fulltime

New

Formal Verification Engineer

The Formal Verification team is dedicated to formal verification. It provides fo...

Location

Canada , Markham

Salary:

155200.00 - 232800.00 CAD / Year

AMD

Expiration Date

Until further notice

Requirements

Combined ASIC/FPGA design and verification experience
Verify complex IPs including I/O virtualization, PCIe Root Complex/End Point, and high-speed inter-chiplet interconnects using advanced formal verification methodologies
Develop and execute formal functional and security verification strategies to ensure industry-leading design quality and coverage
Apply expertise in high-speed I/O protocols, IP verification, and formal verification technologies to validate next-generation semiconductor designs
Drive adoption of cutting-edge formal verification and automation techniques to improve verification efficiency and accelerate closure
Provide technical leadership, mentorship, and methodology guidance across formal verification projects and teams
Demonstrate strong hands-on experience with AI-based formal verification, including AI-assisted property generation, proof optimization, coverage analysis, root-cause debugging, and verification closure
Collaborate closely with architecture, RTL design, DV, and silicon teams from concept through tapeout and post-silicon validation
Strong background in formal property verification (FPV), sequential equivalence checking (SEC/SEQ/SLEC), and/or academic formal methods
Expertise in a formal property language (SVA preferred), abstraction techniques, formal sign-off and commercial formal tools (VC-Formal, JasperGold, Questa Formal, etc.)

Job Responsibility

Collaborating with architects and designers to understand the design intents
Creating and executing formal verification plans for design blocks
Writing and debugging properties to verify the design, analyzing signatures and pushing for the resolution
Optimizing runtime using formal techniques
Collecting and reporting status and progress
Improving formal setups based on feedbacks from reviews, metrics, etc
Leading and coordinating verification activities for a small team
Training and coaching junior engineers
Developing working procedures, flows and infra
Handling complicated formal problems

What we offer

Benefits offered are described: AMD benefits at a glance

Fulltime

New

Asic verification engineer

Designs, analyzes, develops, modifies and evaluates VLSI components and hardware...

Location

United States , Sunnyvale

Salary:

120000.00 - 243000.00 USD / Year

Hewlett Packard Enterprise

Expiration Date

Until further notice

Requirements

Bachelor's or Master's degree in Electrical Engineering, Computer engineering or equivalent
6-10 years of experience in VLSI design, verification, or implementation
Experience with scripting languages (Python, PERL, TCL or equivalent)
Experience with software programming languages (C
C++)
Experience with Verilog/System Verilog
Proficient in UVM methodologies

Job Responsibility

Provide technical expertise and leads project teams of Electronic and VLSI engineers and internal and outsourced development partners responsible for all stages of VLSI design and development for complex products, solutions, and platforms, including design, validation, and testing
Reviews and evaluates designs and project activities for compliance with VLSI technology and development guidelines and standards
provides tangible feedback to improve product quality
Provides VLSI-specific and technical expertise along with the overall architecture design and platform leadership to cross-organization projects, programs, and activities
Provides leadership of project team of other VLSI engineers and internal and outsourced development partners to develop reliable, cost effective and high quality solutions for VLSI prototypes and products
Provides guidance and mentoring to less experienced staff members to set an example of VLSI design and development innovation and excellence
Participates in and provides input on process for selection of future technical leaders
Drives VLSI innovation and integration of new technologies into projects and activities in the design organization

What we offer

Health & Wellbeing
Personal & Professional Development
Unconditional Inclusion

Fulltime

Senior Systems Verification Engineer

This is where your work makes a difference. At Baxter, we believe every person—r...

Location

United States , Round Lake

Salary:

96000.00 - 132000.00 USD / Year

Baxter

Expiration Date

Until further notice

Requirements

Bachelor’s Degree in Mechanical, Electrical, Computer Science, Biomedical Engineering or equivalent
3+ years of relevant industry experience
Medical device industry experience is preferred
Proven organization skills and ability to collaborate with both technical and non-technical personnel
Solid understanding of ISO and/or FDA and other regulatory standards
Knowledge of Design controls, Lifecycle testing processes, MTBF analysis.

Job Responsibility

Contribute to the planning, development and execution of system verification deliverables (test plans, test protocols, test cases, test reports, studies)
Engage in test planning during design and development phases
Contribute to the validation efforts for laboratory equipment supporting infusion system testing
Develop and execute validation protocols, test plans, and reports in alignment with FDA, ISO, and equipment validation best practices
Perform IQ/OQ/PQ activities for lab equipment and ensure complete traceability from requirements through test execution
Contribute to the development and documentation of system requirements, systems architecture and design
Ensure appropriate traceability between system, subsystem, and software verification
Manage the integration of deliverables from subsystem teams, multi-functional teams and external partners
Resolve competing constraints between interrelated functions
Implement configuration and change management through the complete product life-cycle

What we offer

medical and dental coverage that start on day one
insurance coverage for basic life, accident, short-term and long-term disability, and business travel accident insurance
Employee Stock Purchase Plan (ESPP)
401(k) Retirement Savings Plan (RSP)
Flexible Spending Accounts
educational assistance programs
time-off benefits such as paid holidays, paid time off ranging from 20 to 35 days based on length of service
family and medical leaves of absence
paid parental leave
commuting benefits

Fulltime

Principal Systems Verification Engineer

This is where your work saves lives. As a part of Infusion Therapies & Platforms...

Location

United States , Round Lake

Salary:

112000.00 - 154000.00 USD / Year

Baxter

Expiration Date

Until further notice

Requirements

Bachelor's degree in Mechanical, Electrical, Computer Science, Biomedical Engineering or related field
5+ years of relevant industry experience
Strong knowledge of ISO, FDA and other regulatory standards
Knowledge of Design controls, lifecycle testing processes, MTBF analysis
Requires strong organization and communication skills, with the ability to interface with both technical and non-technical personnel
Ability to convince management on courses of action with minimal assistance using both written and verbal methods
Ability to lead teams across multiple sites

Job Responsibility

Lead planning, development and execution of system verification deliverables (test plans, test protocols, test cases, test reports, studies) and provide technical direction to the team
Lead validation efforts for laboratory equipment supporting infusion system testing
Develop and execute validation protocols, test plans, and reports in alignment with FDA, ISO, and equipment validation best practices
Perform IQ/OQ/PQ activities for lab equipment and ensure complete traceability from requirements through test execution
Contribute to the development and documentation of system requirements, systems architecture and design
Create best practices, process improvements and traceability to streamline testing between system, subsystem, and software verification
Implementing configuration and change management through the complete product life cycle, including verification and validation deliverables
Actively communicates and advocates team's capabilities and accomplishments
Create opportunities to automate testing and optimize test processes
Participates and/ or leads design reviews

What we offer

Support for Parents
Continuing Education/ Professional Development
Employee Heath & Well-Being Benefits
Paid Time Off
2 Days a Year to Volunteer
medical and dental coverage that start on day one
insurance coverage for basic life, accident, short-term and long-term disability, and business travel accident insurance
Employee Stock Purchase Plan (ESPP), with the ability to purchase company stock at a discount
401(k) Retirement Savings Plan (RSP), with options for employee contributions and company matching
Flexible Spending Accounts

Fulltime

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