This list contains only the countries for which job offers have been published in the selected language (e.g., in the French version, only job offers written in French are displayed, and in the English version, only those in English).
At Codasip, we’re redefining the future of computing. Following a bold strategic pivot toward cyber-resilient semiconductor architectures, we are building next-generation processors and systems where security is embedded at the very core by design, not as an afterthought. As we expand our portfolio of secure, CHERI-enabled technologies and focus on delivering architecture-first security solutions, there has never been a more exciting time to join. We are embarking on clean-sheet designs and expanding the teams of engineers who can establish high-quality working practices as they explore new ground. Be part of a global team shaping the next era of secure computing where innovation, ownership, and impact go hand in hand.
Job Responsibility
Verify RISC-V processors and extensions
Develop verification solutions (e.g., test benches and test bench components, stimulus generation, formal environments)
Collaborate with other engineers in a team responsible for the delivery of all verification activities related to a component or subsystem from start to finish
Define verification strategies for blocks and sub-systems, identifying and utilising the right tools
Review technical specifications, providing feedback from a verification perspective
Run simulations, hunt bugs and complete root cause analysis of complex issues
Define, estimate, prioritise and track your own work
Track and report verification metrics
Craft automated verification flows
Requirements
Commercial experience with functional processor verification methodologies as applied to CPU or other ASIC verification (simulators, test generation, coverage collection, gate-level simulation, etc.)
Knowledge of verifying CPU architectures or other IP
Fluency and the ability to write clear and concise code in languages like SystemVerilog, Python, C++, Rust, or Go
Past verification ownership of a design block
User knowledge of Linux to enable automation of common tasks
Knowledge of versioning tools (Git, SVN)
Knowledge of RISC-V Architecture
Good knowledge of computer systems and architecture
Analytical thinking and team collaboration skills
Ability to work effectively across teams to debug issues and find root causes