Verification Engineer Job at Teradyne (Alajuela)

Verification Engineer

Teradyne Nextest FPGA Team is looking for experienced verification engineer with...

Location

Costa Rica , Alajuela

Salary:

Not provided

Teradyne

Expiration Date

Until further notice

Requirements

BS in Computer Science, Computer Engineering or Electrical Engineering or related field
English proficiency
8 years of experience with: Digital Design functional verification
Industry standard protocols (e.g. PCIE, AXI)
EDA Tools (e.g. Cadence Xcelium, Simvision)
System Verilog
UVM (Testbench components, development)
Verification IP integration

Job Responsibility

Understand the design requirements from verification perspective
Functional verification using System Verilog and UVM methodology
Create testbench, verification components, and tests
Create self-checking verification environment with data checkers and assertions
Debug failures using waveforms and test log reports
Drive verification completion with 100% functional coverage and code coverage
Interacting with FPGA design, software and hardware team for test strategies and debugging failures

What we offer

Teradyne offers a variety of robust health and well-being benefit programs, including medical, dental, vision, life and health insurance, paid vacation & holidays, tuition assistance programs, and more

Verification Engineer

We are seeking skilled SoC (System-on-Chip) ARM Power architecture, Soc clock an...

Location

India , Noida

Salary:

Not provided

ARM

Expiration Date

Until further notice

Requirements

3 - 6 years of proven experience in working on SoC verification environments across Power verification involving multiple power islands and clock and reset verification
Knowledge of assembly language (preferably ARM), C/C++ and hardware verification languages (e.g. SystemVerilog), shell programming/scripting (e.g. Tcl, Perl, Python etc.)
Experience in one or more of various verification methodologies – UVM/OVM, formal, low power
Good knowledge and working verification experience in Arm M class CPU Processors
Good experience in handling Power aware verification with complex power architecture
Exposure to all stages of verification: requirements collection, creation of test plans, testbench implementation, test cases development, documentation and support
Understanding of the fundamentals of Arm system architectures
Experience with various front-end verification tools - Dynamic simulation tools, Static Simulation tools, UPF, and Debuggers
Experience in working and debugging Soc in DFT mode
Exposure to various front-end verification tools - Questa, VCS, Jasper Gold, Verdi

Job Responsibility

Writing test plans, defining test methodologies, and completing functional verification to the required quality levels and schedules
Leading a team of engineers to own and power, clk/rst verification for a complex IoT chip
Collaborate with engineers in architecture, design, verification, implementation, modeling, performance analysis, silicon validation, FPGA and board development and build a functional verification strategy
Support mentor junior team members

What we offer

Health and Wellness
Work and Life Success
Financial Rewards
Development and Support

Senior Lead Verification Engineer (Leadership role)

The Infinity Fabric transport layer verification team is looking for an experien...

Location

India , Bangalore

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

Proficient in IP or Sub-system level ASIC verification
Architected and developed complex verification environments and infrastructure, including scripting using Perl, Ruby, Make, or similar
Exposure to RTL design, software development, formal verification, or other related domains
Experience in UVM TestBench Development for complex designs preferred
15+ years of industry experience is preferred
Bachelor’s or master’s degree in Electronics or Electrical or Computer engineering

Job Responsibility

Develop and enhance System Verilog / UVM-based testbenches to verify new features for client, server, graphics, and semi-custom interconnects
Interact with architects, RTL designers, performance engineers, and post-silicon validation engineers to develop deep expertise in the Infinity Fabric architecture
Understand TestBench Architecture and develop expertise in TestBench Verification Components
Mentor junior engineers

Senior Design Verification Engineer – Security IP

WHAT YOU DO AT AMD CHANGES EVERYTHING. At AMD, our mission is to build great pro...

Location

India , Bangalore

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

BSc with a minimum of equivalent 5 years relevant experience
or MSc with a minimum of equivalent 3 years
or PhD in a directly related research area and a minimum of 1 year
A minimum of equivalent 10 years relevant experience if as advanced level team members
Proven understanding of MP subsystem and/or common hardware datapath accelerator architectures as well as deep knowledge of applicable state-of-art verification methodology and best practices, if as advanced level team members
Proficient in System Verilog, object oriented programming, and scripting (using Ruby, Perl, Python and Makefile)
Proven skills in creating UVC and other UVM components. Experience with C-DPI and Formal Verification techniques are valuable assets
Excellent understanding of standard bus/interface protocols (i.e. AXI, AHB, AMBA)
Proven experience with ASIC verification tools: simulation, debugging, linting, power aware simulation, etc.
Relevant design domain specific knowledge and technical leadership capability required for advanced level candidates

Job Responsibility

Develop and maintain block level IP and MP subsystem verification architecture, testbenches, test methodology and infrastructure
Develop and debug test plans using SystemVerilog/UVM constrained-random test methodology, C-DPI directed test methodology, formal proof verification methodology, and using object-oriented programming (OOP) techniques to implement/maintain testbenches and tests
Triage regressions, debug simulations, analyze coverage, work/resolve technical issues with design, verification and other teams to achieve verification closure
Participate in MP subsystem specification, influence IP micro-architecture development (design for verification aspect), design and execute reusable test methodology across individual MP subsystems
Debug and solve integration issues with SoC Integration and SoC DV teams
Provide technical leadership in verification methodology development and critical problem resolution if as advanced level team members
Provide project execution leadership in term of technical assignment ownership, technical mentorship, task planning through divide and conquer, task progress reporting and forecasting if as advanced level team members

Fulltime

New

Android Engineer, Verification

We are looking for a seasoned Android Engineer to join the Verification team and...

Location

Poland; Romania , Warsaw; Bucharest

Salary:

Not provided

Bolt

Expiration Date

Until further notice

Requirements

Comfortable making data-driven decisions that positively impact the business
Enjoy taking ownership of initiatives and driving them through to completion, including monitoring their success after launch
Experience releasing high-quality mobile features across multiple Android versions, including experience with testing and automation frameworks
Care deeply about building clean, simple, secure, and maintainable solutions
Solid understanding of algorithms and data structures
Using AI daily is a baseline expectation for everyone
Experience with camera APIs, media capture, on-device ML, or mobile SDK development is a plus

Job Responsibility

Designing, developing, A/B testing, and deploying solutions that improve the user journey across verification flows
Evolving our Verification SDK - the mobile entry point that captures documents, biometrics, and other verification media for Bolt's verticals
Working closely with backend and machine learning engineers to define and implement integrations for document capture, on-device validation, and biometric checks
Thoroughly testing solutions to ensure quality and reliability across both standard and edge-case scenarios, including a wide range of devices, cameras, and document types
Building a deep understanding of our products and their impact on business metrics and end users, while contributing ideas and feedback to the product roadmap
Leading feature development from idea to measurable impact for end users

What we offer

Rewarding salary and stock option package
Flexibility of working in a hybrid mode with a minimum of 3 days in the office each week
Wellness perks for physical and mental health

Fulltime

New

Hardware Verification Engineer

This individual will serve as a Hardware Verification Engineer for QA test envir...

Location

United States , North Reading

Salary:

67400.00 - 107800.00 USD / Year

Teradyne

Expiration Date

Until further notice

Requirements

Strong software skills with a greater than 3.0 GPA
Degree in Bachelors Degree program - Acceptable majors Electrical Engineer or Computer Science or Computer Engineering
Between 0 and 2 year of experience in related fields
Basic understanding of test techniques/methodologies
Knowledge of statistical analysis techniques
Programming experience in object oriented software. (C++, and C# is a plus)
Experience with version control software. (Rational Software Clear Case is a plus)
Experience in Microsoft windows and Microsoft applications (Microsoft .NET infrastructure is a plus)
Must be available to work on site at our North Reading, MA facility
Local to position location

Job Responsibility

Serve as a Hardware Verification Engineer for QA test environment and associated tools for internal development across the UltraFLEX, UltraFLEXPlus, J750 and ETS platforms
Develop high speed digital test concepts, coding the tests, debugging the tests, verifying the tests and deploying the tests to the production team
Programming in C#/.NET and C++ while working in a local team environment as well as communicating with an extended team based in Agoura Hills, Buffalo Grove, and Costa Rica

What we offer

Medical, dental, vision, Flexible Spending Accounts, retirement savings plans, life and disability insurance, paid vacation & holidays, tuition assistance programs
Discretionary bonus based on financial performance

Fulltime

Infinity Fabric Senior Staff Verification Engineer

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great pr...

Location

United States , Santa Clara

Salary:

200000.00 - 300000.00 USD / Year

AMD

Expiration Date

Until further notice

Requirements

Proficient in IP level ASIC verification
Proficient in debugging firmware and RTL code using simulation tools
Proficient in using UVM testbenches and working in Linux and Windows environments
Experienced with Verilog, System Verilog, C, and C++
Developing UVM based verification frameworks and testbenches, processes and flows
Automating workflows in a distributed compute environment
Exposure to simulation profile, efficiency improvement, acceleration, HLS tools/process
Good understanding and hands-on experience in the UVM concepts and SystemVerilog language
Good working knowledge of SystemC and TLM with some related experience
Scripting language experience: Perl, Ruby, Makefile, shell preferred

Job Responsibility

Define and drive verification strategy for complex GPU features or subsystems with cross‑project and cross‑product impact
Partner with architects, RTL, and firmware leads to influence feature definition, implementation approach, and verification readiness early in the design cycle
Own verification planning and execution for technically critical areas, including risk identification, trade‑off analysis, and mitigation strategies
Lead development of robust, scalable verification environments and methodologies, including directed and constrained‑random testing using SystemVerilog and UVM
Solve complex, ambiguous verification challenges, often requiring new approaches or extensions to existing processes and infrastructure
Analyze functional and code coverage at a system level, driving coverage closure strategies that balance quality, schedule, and compute efficiency
Drive improvements to verification processes, tools, and workflows that increase productivity, quality, or execution efficiency across teams
Coordinate and technically lead small verification efforts within larger programs, aligning stakeholders and delivering on shared objectives
Mentor and coach junior and senior engineers, acting as a go‑to technical resource and influencing best practices across the organization

What we offer

Benefits offered are described: AMD benefits at a glance

Fulltime

Design Verification Engineer

The focus of this role is to plan, build, and execute the verification of new an...

Location

Canada , Markham

Salary:

128000.00 - 192000.00 CAD / Year

AMD

Expiration Date

Until further notice

Requirements

Bachelors or Masters degree in computer engineering/Electrical Engineering
Proficient in IP level ASIC verification
Proficient in debugging firmware and RTL code using simulation tools
Developing UVM based verification frameworks and testbenches, processes and flows
Proficient in using UVM testbenches and working in Linux and Windows environments
Experienced with Verilog, System Verilog, C, and C++
Assembly-level debugging ability
Scripting proficiency in Perl or Python (shell/Makefile/Ruby beneficial)
Proficient in using UVM testbenches and working in Linux and Windows environments
Practical experience with functional and code coverage analysis and closure

Job Responsibility

Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified
Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases
Estimate the time required to write the new feature tests and any required changes to the test environment
Build the directed and random verification tests
Debug test failures to determine the root cause
work with RTL and firmware engineers to resolve design defects and correct any test issues
Review functional and code coverage metrics – modify or add tests or constrain random tests to meet the coverage requirements

Fulltime

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