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We are seeking a skilled Verification Engineer with expertise in AXI/APP/AHB interface CPU/Memory controller verification, specifically for LPDDR. The ideal candidate will have a strong background in SystemVerilog (SV) and Universal Verification Methodology (UVM). This role requires a detail oriented individual who can work collaboratively within a team to ensure the highest quality of verification processes.
Job Responsibility:
Develop and execute verification plans for AXI/APP/AHB interfaces and LPDDR memory controllers
Utilize SystemVerilog and UVM methodologies to create testbenches and verification environments
Perform functional verification, including writing and executing test cases, debugging, and analyzing results
Collaborate with design engineers to understand specifications and provide feedback on design improvements
Participate in design reviews and provide insights on potential verification challenges
Document verification processes, results, and methodologies for future reference
Mentor junior engineers and provide guidance on best practices in verification
Requirements:
Bachelor’s or Higher Degree
5-7 years of experience in VLSI verification, specifically with a focus on UVM
Strong expertise in VLSI verification using UVM
Proficient in SystemVerilog (SV) for developing testbenches
Experience with AXI/APP/AHB protocols and LPDDR memory controllers
Solid understanding of digital design principles and verification methodologies
Ability to analyze complex designs and develop effective verification strategies
Strong analytical and problem solving skills
Excellent communication and teamwork abilities
Nice to have:
Familiarity with other verification tools and methodologies
Experience in scripting languages such as Python or Perl for automation
Knowledge of formal verification techniques
Experience with coverage driven verification and assertion based verification