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This technical role is Client Post-Silicon features IO validation and enablement at the silicon IP level up through IP, integration, and system levels on AMD client products. This individual will be primarily responsible for leading the IO component AVL validation, interfacing with IP design, debug, BIOS/firmware, and platform design groups to develop, optimize and execute validation test plans for client products from pre-silicon validation plan to post-silicon bring-up/validation, debug feature issues, and maintain validation infrastructure to achieve product deliver milestones.
Job Responsibility:
Perform USB IP /PCIe functional validation at system level and IP/block level in pre-silicon and/or post-silicon environments
Develop validation plans, test cases, and test environments based on design specifications and architecture documents
Execute validation tests, analyze results, and ensure comprehensive coverage for USB IP and related system components
Validate and debug features and interoperability involving USB and PCIe subsystems on x86-based platforms
Work closely with design, architecture, firmware, and software teams to identify root-cause, and resolve functional issues
Participate in automation and improvement of validation flows, AI tools, and methodologies
Execute and drive success of programs with multiple projects on the goal
Requirements:
Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related field
Solid understanding of x86 architecture, including system-level components and interactions
Strong knowledge of USB & PCIe Spec and protocol (e.g., USB 2.0/3.x/USB4. TBT)
Hands-on experience in system-level and/or IP-level validation (post-silicon)
Experience with debug and issue root-cause, including use of common debug tools (Windows ETL, logic analyzers, protocol analyzers, waveform viewers, etc.)
Familiarity with Linux operating system, including basic shell usage, scripting, and driver/application bring-up
Experience with pre-silicon verification/validation environments (e.g., simulation, emulation, FPGA prototyping) or post-silicon validation labs
Experience with validation frameworks, test infrastructure
Knowledge of system-level performance, power, and reliability validation concepts for I/O subsystems
Good verbal and written communication skills in English
Nice to have:
Familiarity with AI applications, or hands-on experience in developing AI-driven tools/workflows for validation or related domains