Tlm Developer Job at Realign (Toronto)

Virtual Platforms & SoC Modeling Engineer

Meta’s Silicon Engineers are at the forefront of innovation, driving the design ...

Location

United States , Sunnyvale

Salary:

146000.00 - 209000.00 USD / Year

New

Runway Safety Product Manager

The jobholder will act as Runway Safety Product Manager, and will notably active...

Location

France , Toulouse

Salary:

Not provided

NAVBLUE Limited

Expiration Date

Until further notice

Requirements

Master’s degree in Aeronautical Engineering or equivalent
Demonstrated strong analytical and technical skills
Technical: Avionics system, Aircraft performance
Coding : Python, Matlab, Simulink, Git.
Experience in project management (Stakeholders and suppliers management)
A proven Experience in ROPS (Runway Overrun Prevention System) avionics function and Aircraft Performance Development)
Recognized for your agility and analysis skills for complex technical topics.
Demonstrate Strong communication skills
Ability to travel internationally (3-5 Domestic and International travels a year)
> +5 Years of experience

Job Responsibility

Ensuring coordination on ROPS support with Airbus / Airlines
Supporting ROPS operators and ensuring technical support (entry into service) on all airbus aircraft.
Lead & Analyze in-service events, evaluate airworthiness risk and collaborate with Airbus performance team
Proposing new ways of working on In service events related to a new tool for the analysis
Ensuring coordination to the development of a new monitoring for the ROPS function on the A320 Family.
Be the project lead for Taxiway Landing Monitor (TLM) function Controlled Entry Into Service (CEIS) jointly with Airbus
Participating in meetings and reviews with Airbus engineering teams to ensure a good level of communication between NAVBLUE and Airbus Design Office regarding in-service feedback from Airbus ROPS operators.
Act as backup in the team on another runway safety project called BACF (Braking Action Computation Function) / Runway Sense digital platform

What we offer

Work-Life Balance & Flexibility
Flexible working hours with a hybrid model (3 days per week in our Blagnac office).
25 annual paid leave days + Collective and individual JRTT (proportional to working time).
A 6th week of paid leave (proportional to working time).
Generous 12-day "family reason absence package."
Family & Health Support
5 additional full-pay days for maternity, paternity, and adoption leave.
Comprehensive Health Insurance plan.
3 extra paid annual leave days for employees with RQTH status.
Financial Wellbeing & Savings

Fulltime

Runway Safety Specialist

The jobholder will act as Runway Safety Specialist, and will notably actively co...

Location

France , Toulouse Area

Salary:

Not provided

Airbus

Expiration Date

April 01, 2026

Requirements

Master’s degree in Aeronautical Engineering or equivalent
Demonstrated strong analytical and technical skills
Technical: Modeling, Machine learning, Algorithm
Coding: Python, Matlab, Simulink, Git
Experience in project management (Stakeholders and suppliers management)
A proven Experience in ROPS (Runway Overrun Prevention System) avionics function and Aircraft Performance Development
Recognized for your agility and analysis skills for complex technical topics
Demonstrate Strong communication skills
Ability to travel internationally (3-5 Domestic and International travels a year)
Preferably +5 Years of experience

Job Responsibility

Ensuring coordination on ROPS support with Airbus / Airlines
Supporting ROPS operators and ensuring technical support (entry into service) on all airbus aircraft
Analyze in-service events, evaluate airworthiness risk and collaborate with Airbus performance team
Proposing new ways of working on In service events related to a new tool for the analysis
Ensuring coordination to the development of a new monitoring for the ROPS function on the A320 Family
Be the project lead for Taxiway Landing Monitor (TLM) function Controlled Entry Into Service (CEIS) jointly with Airbus
Participating in meetings and reviews with Airbus engineering teams to ensure a good level of communication between NAVBLUE and Airbus Design Office regarding in-service feedback from Airbus ROPS operators
Act as backup in the team on another runway safety project called BACF (Braking Action Computation Function) / Runway Sense digital platform

What we offer

Work-Life Balance & Flexibility: Flexible working hours with a hybrid model (3 days per week in our Blagnac office)
25 annual paid leave days + Collective and individual JRTT (proportional to working time)
A 6th week of paid leave (proportional to working time)
Generous 12-day "family reason absence package"
Family & Health Support: 5 additional full-pay days for maternity, paternity, and adoption leave
Comprehensive Health Insurance plan
3 extra paid annual leave days for employees with RQTH status
Financial Wellbeing & Savings: Success sharing (intéressement) and profit sharing (participation) schemes
Monthly seniority bonus for all employees with 3+ years of service
Access to Airbus Group saving plans (PEG) including investment in Airbus shares after 3+ months of service

Fulltime

Controller Modelling Developer – Virtual ECU Prototyping

The Virtualization and SIL Integration team at General Motors is a highly techni...

Location

Canada , Markham

Salary:

90600.00 - 136400.00 USD / Year

General Motors

Expiration Date

Until further notice

Requirements

Minimum 1 - 3 years of relevant professional engineering experience
Minimum of 1+ years of experience in SystemC, Transaction Level Modeling (TLM 2.0), and SCML
Proficiency in off the shelf EDA toolchains such as Synopsys Virtualizer and ASTC vLAB
Expertise in various programming languages (C, C++, Python)
Experience in low-level input/output driver development and debugging
Knowledge of electronic control modules and embedded control systems
Knowledge of ARM based microcontrollers
Software integration, compiler and linker file comprehension expertise
Knowledge of AUTOSAR and Automotive Cyber Security
Knowledge in automotive communications (e.g. CAN, LIN, SPI, I2C, UART)

Job Responsibility

Create SystemC TLM2.0 models of microcontrollers, asics, drivers, modules, switches, timers, transceivers, etc.
Integrate microcontroller and peripheral models into full Level 4 virtual ECUs
Debug model and integration bugs and issues
Work cross-functionally with Design Release Engineers, Tier 1 suppliers, and software engineers to develop vECUs
Integrate production software into vECUs
Validate and verify vECU functions as expected and executes production software as intended
Collaborate with software developers to root cause and solve low-level, basic software and application software issues found in the virtual environment
Debug integrated production software as needed
Develop script-based engineering workarounds to bridge virtual model limitation gaps
Work cross-functionally with Simulation Integration Engineers to support the integration of vECUs into virtual environments

What we offer

Paid time off including vacation days, holidays, and supplemental benefits for pregnancy, parental and adoption leave
Healthcare, dental, and vision benefits
Life insurance plans to cover you and your family
Company and matching contributions to a Defined Contribution Pension plan to help you save for retirement
GM Vehicle Purchase Plan for you, your family and friends

Fulltime

New

Senior ASIC-FPGA Verification Engineer

At Boeing, we innovate and collaborate to make the world a better place. We’re c...

Location

India , Bengaluru

Salary:

Not provided

Boeing

Expiration Date

April 04, 2026

Requirements

Bachelor degree in Engineering, Engineering Technology (including Manufacturing Technology, Micro Electronics, VLSI/CAD/Embedded systems), Computer Science, Data Science, Mathematics, Physics, Chemistry, or non-US equivalent qualifications directly related to the work statement
13 to 17 years of experience in Digital Functional verification for both ASIC and FPGA at IP, Subsystem and System level as a Lead or Verification Architect
8+ years of experience in leading and owning verification Activities for Multiple ASIC and FPGA product Tape outs
7+ years of experience in Developing and mentoring Verification engineers
5+ years of Hands-on domain experience on PCIe (Transaction layer) and Ethernet (Mac Layer)
Multiple Verification tape out experience in ASIC and FPGA products
5+ years of experience in doing UVM based Testbench Architecture for PCIe and Ethernet across IP/Subsystem and system level for multiple projects in ASIC and FPGA

Job Responsibility

Use high-level architectural documentation along with algorithm description and implement functions for test bench architecture and test plan using UVM for IP, Subsystem and System level verification
Develop reusable testbench components like scoreboards, checkers, reference models along with UVC using SV and UVM
Own quality of deliverables for verification across multiple milestones for FPGA/ASIC life cycle
Architect Reusable Verification components, which can be used across FPGA/ASIC life cycle
Lead, drive and collaborate technical reviews with Validation, Design and System Architecture cross functional teams
Support Architecture exploration at system level using System C or TLM models using SV-UVM
Verification Domain expert for PCIe and Ethernet protocols
Identifies, tracks and status technical performance measures to measure progress and ensure compliance with verification requirements
Develop Junior engineers, solve simple to complex technical problems in verification
Support in Technical strategy in collaboration with Engineering management for the FPGA/ASIC V&V

What we offer

Competitive base pay and incentive programs
Industry-leading tuition assistance program pays your institution directly
Resources and opportunities to grow your career
Up to $10,000 match when you support your favorite nonprofit organizations
Relocation based on candidate eligibility

Fulltime

ASIC Engineer, Architecture

Meta Platforms, Inc. (Meta), formerly known as Facebook Inc., builds technologie...

Location

United States , Sunnyvale

Salary:

208936.00 - 241560.00 USD / Year

Low Power Design Verification Engineer

The focus of this role is to develop, execute, debug tests and methodologies for...

Location

United States , Boxborough

Salary:

139360.00 - 209040.00 USD / Year

AMD

Expiration Date

Until further notice

Requirements

SoC level ASIC verification experience
Experience with multiple SoC tape-outs taken to production
Hands on experience of Low Power design and verification methodologies (e.g., UPF, power domains, multi-voltage)
NPU/AI processor knowledge
Proficient in debugging firmware and RTL code using simulation tools
Proficient in developing and using UVM based verification frameworks and testbenches, processes and flows in both Linux and Windows environments
Automating workflows in a distributed compute environment
Experienced with Assembly, Verilog, System Verilog, C, C++
Good understanding and hands-on experience in the UVM concepts
Good working knowledge of SystemC and TLM with some related experience

Job Responsibility

Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified
Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases
Estimate the time required to write the new feature tests and any required changes to the test environment
Build the directed and random verification tests
Debug test failures to determine the root cause
work with RTL and firmware engineers to resolve design defects and correct any test issues
Review functional and code coverage metrics – modify or add tests or constrain random tests to meet the coverage requirements

Fulltime

New

MTS Silicon Design Engineer

The focus of this role is to plan, build, and execute the verification of new an...

Location

India , Hyderabad

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

Proficient in IP level ASIC verification
Proficient in debugging firmware and RTL code using simulation tools
Proficient in using UVM testbenches and working in Linux and Windows environments
Experienced with Verilog, System Verilog, C, and C++
Graphics pipeline knowledge
Developing UVM based verification frameworks and testbenches, processes and flows
Automating workflows in a distributed compute environment
Exposure to simulation profile, efficiency improvement, acceleration, HLS tools/process
Strong background in the C++ language, preferably on Linux with exposure to Windows platform
Good understanding and hands-on experience in the UVM concepts and SystemVerilog language

Job Responsibility

Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified
Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases
Estimate the time required to write the new feature tests and any required changes to the test environment
Build the directed and random verification tests
Debug test failures to determine the root cause
work with RTL and firmware engineers to resolve design defects and correct any test issues
Review functional and code coverage metrics – modify or add tests or constrain random tests to meet the coverage requirements

Tlm Developer

Realign

Location:
Canada , Toronto

Category:
IT - Software Development

Contract Type:
Not provided

Salary:

Job Description:

Requirements:

Additional Information:

Job Posted:
March 21, 2026

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