Technologist, ASIC Development Engineering (RTL Design and SOC) Job at Sandisk (Bengaluru)

Technologist, ASIC Development Engineering (RTL Design and SoC architecture, Lint)

Are you ready to push the boundaries of what's possible in technology? Join the ...

Location

India , Bengaluru

Salary:

Not provided

Sandisk

Expiration Date

Until further notice

Requirements

Bachelor’s or master’s degree in electrical engineering, Computer Engineering, or a related field with 14-18 years of experience
Proven experience in ASIC RTL design, with a strong grasp of Verilog/System Verilog
Strong understanding of SoC architecture, AMBA protocols (AXI/AHB/APB), interconnects and peripherals for debug
Prior knowledge of Power Intent format (UPF) and Timing Constraints (SDC) is a must
Proficiency in scripting languages (e.g., Python, TCL) for automation
Hands-on with EDA tools (simulation, lint, CDC, synthesis, formal verification)
Strong problem-solving skills and the ability to thrive in a dynamic environment
Excellent communication and teamwork abilities

Job Responsibility

Innovate, implement, and verify RTL code for complex ASICs
Own SoC subsystems related to CPU complex, DDR, Host, Flash, Debug, Clocks, resets, Power domains etc. for top of the line flash controllers
Ensure robust design methodologies including Lint, CDC, RDC, CLP and FC-Elab
Utilize advanced AI-driven tools, including GitHub Copilot, to streamline the design process
Collaborate with DFT, PD, Hardware and Firmware teams for delivering the most optimal solution
Lead design reviews and provide mentorship to junior engineers
Work along side with the SoC Managers and SoC Leads to deliver best-in-class solution
Stay abreast of the latest industry trends and emerging technologies in AI and ASIC design

Fulltime

Technologist, ASIC Development Engineering (PD Methodology & CAD Flow Architect/Lead)

Sandisk’s ASIC team builds state-of-the-art memory controllers that power world-...

Location

India , Bengaluru

Salary:

Not provided

Sandisk

Expiration Date

Until further notice

Requirements

10+ years of experience in Physical Design, PD Methodology, or CAD for advanced ASICs
Deep, hands-on understanding of complete PD flow, including: Synthesis, Logical Equivalence Checking (LEC), DFT insertion and integration, Place & Route, Static Timing Analysis (STA), Physical Verification, EM/IR analysis
Strong grasp of inter-dependencies across the PD flow and their impact on design convergence and PPA
Proven experience architecting PD methodologies and flows for complex SoCs or IPs on advanced nodes
M.Tech in VLSI Design or a related field (or equivalent industry experience)
Proficiency in scripting and automation using TCL, Perl, and/or Python
Experience working in multi-project, high-complexity environments with tight schedules

Job Responsibility

Lead and mentor the PD Methodology/CAD team to deliver scalable, production-ready flows and innovative solutions across multiple programs
Design and architect end-to-end PD methodologies (RTL to GDS) for advanced technology nodes, ensuring correctness, robustness, and scalability
Drive continuous improvement in PPA (Power, Performance, Area) and turnaround time through flow optimization, automation, and best practices
Work closely with foundry partners to understand node-specific challenges (design rules, variability, EM/IR, signoff requirements) and develop correct-by-construction solutions
Collaborate with IP teams, RTL design, DFT, and signoff teams to address cross-domain optimization challenges and enable smooth design convergence
Develop “shift-left” and “push-up” methodologies to detect and resolve issues early in the design cycle, improving predictability and schedules
Deliver high-quality, signoff-clean flows with strong emphasis on reliability, yield, and manufacturability
Leverage AI/ML techniques to improve quality, debug efficiency, predict design issues, and enhance overall productivity
Foster a culture of technical excellence and innovation, encouraging the team to develop novel solutions for next-generation challenges

Fulltime

Technologist, ASIC Development Engineering

We are looking for a highly skilled and experienced individual for SoC PD lead p...

Location

India , Bengaluru

Salary:

Not provided

Sandisk

Expiration Date

Until further notice

Requirements

Bachelor’s or master’s degree in electrical engineering, Computer Engineering, or a related field
A minimum of 13 to 15 years of experience in leading RTL to GDSII implementation effort across various SoCs
Proven ability in technically leading a small/medium-sized team for executing projects preferred
Hands-on experience on the entire PD Flow from RTL to GDSII
Should have a good understanding of Floor planning, Power Planning, Placement & Optimization, CTS, Routing, Design Convergence, and Sign-off with in-depth expertise in at least one of these domains
Working knowledge about OCV, MM/MC optimization and multi-power designs (Level shifters, Isolation cells, etc)
Exposure to static timing analysis fixes including automated ECO generation
Strong in areas on CTS, Power, Bump planning, Floorplan
Experience with tools (e.g., Synopsys FusionCompiler, PrimeTime, Cadence Innovus, Constraints Manager, Redhawk, Calibre etc.) and methodologies
Library preparation in any environment (Synopsys, Cadence, etc)

Job Responsibility

To be responsible for leading RTL-to-GDSII SoC implementation effort
To collaborate with cross-functional teams, including Design, Verification, Analog, DFT, SIPI etc
To develop and guide the team members in their work, enhancing their technical capabilities and increasing productivity
To ensure process compliance during project execution and enable / participate in technical discussions/reviews
To prepare and submit status reports for minimizing exposure and risks on the project or closure of escalations
Stay abreast of industry trends and emerging technologies in related fields, and incorporate best practices into the team’s workflow
Foster a culture of innovation, collaboration, and continuous improvement

Fulltime

Technologist, ASIC Development Engineering (PD Methodology & CAD Flow Architect/Lead)

Sandisk’s ASIC team builds state-of-the-art memory controllers that power world-...

Location

India , Bengaluru

Salary:

Not provided

Sandisk

Expiration Date

Until further notice

Requirements

10+ years of experience in Physical Design, PD Methodology, or CAD for advanced ASICs
Deep, hands-on understanding of complete PD flow, including: Synthesis, Logical Equivalence Checking (LEC), DFT insertion and integration, Place & Route, Static Timing Analysis (STA), Physical Verification, EM/IR analysis
Strong grasp of inter-dependencies across the PD flow and their impact on design convergence and PPA
Proven experience architecting PD methodologies and flows for complex SoCs or IPs on advanced nodes
M.Tech in VLSI Design or a related field (or equivalent industry experience)
Proficiency in scripting and automation using TCL, Perl, and/or Python
Experience working in multi-project, high-complexity environments with tight schedules

Job Responsibility

Lead and mentor the PD Methodology/CAD team to deliver scalable, production-ready flows and innovative solutions across multiple programs
Design and architect end-to-end PD methodologies (RTL to GDS) for advanced technology nodes, ensuring correctness, robustness, and scalability
Drive continuous improvement in PPA (Power, Performance, Area) and turnaround time through flow optimization, automation, and best practices
Work closely with foundry partners to understand node-specific challenges (design rules, variability, EM/IR, signoff requirements) and develop correct-by-construction solutions
Collaborate with IP teams, RTL design, DFT, and signoff teams to address cross-domain optimization challenges and enable smooth design convergence
Develop “shift-left” and “push-up” methodologies to detect and resolve issues early in the design cycle, improving predictability and schedules
Deliver high-quality, signoff-clean flows with strong emphasis on reliability, yield, and manufacturability
Leverage AI/ML techniques to improve quality, debug efficiency, predict design issues, and enhance overall productivity
Foster a culture of technical excellence and innovation, encouraging the team to develop novel solutions for next-generation challenges

Fulltime

Technologist, ASIC Development Engineering

Are you ready to push the boundaries of what's possible in technology? Join the ...

Location

India , Bengaluru

Salary:

Not provided

Sandisk

Expiration Date

Until further notice

Requirements

Bachelor’s or master’s degree in electrical engineering, Computer Engineering, or a related field with 14-18 years of experience
Proven experience in ASIC RTL design, with a strong grasp of Verilog/System Verilog
Strong understanding of SoC architecture, AMBA protocols (AXI/AHB/APB), interconnects and peripherals for debug
Prior knowledge of Power Intent format (UPF) and Timing Constraints (SDC) is a must
Proficiency in scripting languages (e.g., Python, TCL) for automation
Hands-on with EDA tools (simulation, lint, CDC, synthesis, formal verification)
Strong problem-solving skills and the ability to thrive in a dynamic environment
Excellent communication and teamwork abilities

Job Responsibility

Innovate, implement, and verify RTL code for complex ASICs
Own SoC subsystems related to CPU complex, DDR, Host, Flash, Debug, Clocks, resets, Power domains etc. for top of the line flash controllers
Ensure robust design methodologies including Lint, CDC, RDC, CLP and FC-Elab
Utilize advanced AI-driven tools, including GitHub Copilot, to streamline the design process
Collaborate with DFT, PD, Hardware and Firmware teams for delivering the most optimal solution
Lead design reviews and provide mentorship to junior engineers
Work along side with the SoC Managers and SoC Leads to deliver best-in-class solution
Stay abreast of the latest industry trends and emerging technologies in AI and ASIC design

Fulltime

Senior Quantum Foundry Technologist & Library Specialist

At Microsoft Quantum, we aim to empower science and scientists to solve the worl...

Location

United States , Redmond

Salary:

119800.00 - 258000.00 USD / Year

Microsoft Corporation

Expiration Date

Until further notice

Requirements

Doctorate in Physics, Engineering, or related field AND 1+ year(s) experience in industry or in a research and development environment, could include completion of a post doctoral research position
OR Master's Degree in Physics, Engineering, or related field AND 4+ years experience in industry or in a research and development environment
OR Bachelor's Degree in Physics, Engineering, or related field AND 6+ years experience in industry or in a research and development environment
OR equivalent experience
Ability to meet Microsoft, customer and/or government security screening requirements are required for this role
Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter
Citizenship & Citizenship Verification: This role will require access to information that is controlled for export under export control regulations
As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their U.S. permanent residency or other protected status for assessment of eligibility to access the export-controlled information
Doctorate in Physics, Engineering, or related field AND 3+ years experience in industry or in a research and development environment, could include completion of a post doctoral research position
OR Master's Degree in Physics, Engineering, or related field AND 6+ years experience in industry or in a research and development environment

Job Responsibility

Audit external foundries to find a suitable partner for long-term engagement for Microsoft quantum/cryo silicon programs
Evaluate their solutions for materials/process tailoring to match our needs
Create long-term evolution plans with vendors for evolving process needs for future quantum products
Lead technical interactions with external foundries both in pre-silicon design and post silicon development as well as continuous improvement for Yield and performance during production manufacturing stage to ensure Best-in-class Microsoft first-party silicon
Find / define design development libraries and re-characterizations for standard cells and analog design PDKs at cryo temperatures
Define and design engineering structure in testchip for technology interception and enablement including data collection, analysis and model-silicon characterization
Compile and analyze data using common statistical techniques and effectively present key results along with recommended actions
practice continuous improvement and yield optimization and analyze products to ensure manufacturability and data sheet compliance
Embody our culture and values

Fulltime

New

Process Specialist / Business Analyst

Are you an experienced process expert looking for your next challenge? Our clien...

Location

Australia , Brisbane

Salary:

Not provided

Randstad

Expiration Date

July 15, 2026

Requirements

Proven experience leading continuous improvement designed to deliver successful change and transformation in a complex environment
High-level research, analytical, and problem-solving skills, with the ability to identify issues and risks and work collaboratively to develop solutions
Demonstrated experience in and understanding of business process management methods, practices, and BPM tools such as BPMN, IBM Blueworks, or SAP Signavio
Proven leadership in customer and employee experience (EX and CX), along with the ability to negotiate and influence stakeholders across all levels
Proven success in developing and maintaining relationships, influencing, making decisions, and motivating others towards achieving key work priorities
Must be a Brisbane based candidate with unlimited working rights

Job Responsibility

Support the implementation, embedment, and maturing of the Process Excellence (PEx) Framework to improve business process management maturity
Support, oversee, and coordinate group-wide reviews of processes, service standards, and performance to ensure alignment with best practice and consistent end-to-end service experience
Develop and implement strategies that enhance the performance, productivity, and quality of business capabilities and business services
Develop and maintain business process management documents, tools, resources, and training materials to build organisational knowledge and awareness
Provide advice, guidance, and direction to stakeholders at all levels on appropriate BPM priorities to ensure responsible investment and benefit realisation

What we offer

Access to a Udemy license for ongoing learning and continuous professional development
Access to exclusive discounts across various platforms
Discounts on private health funds
3 payruns a week

Fulltime

New

Head of Federal Affairs - Brisbane 2032

A new and exciting opportunity has emerged with the Brisbane 2032 Olympic and Pa...

Location

Australia , Brisbane

Salary:

Not provided

Randstad

Expiration Date

July 15, 2026

Requirements

Strong knowledge of key policy and legislative areas related to Federal government impact on the Games
Demonstrated experience in influencing stakeholders and diplomatic approach to problem solving and management of key initiatives
Demonstrated experience and track record in development of strong relationships with Federal government stakeholders
Excellent oral presentation, negotiation and engagement skills including a high level of cross-cultural capability
Desirable though not essential is a knowledge of policy areas relevant to the Games including industrial relations, immigration, security, quarantine

Job Responsibility

Drive Brisbane 2032’s Federal Government engagement strategy by building strong Commonwealth relationships to ensure alignment on our key priorities
In this role, you will also partner with the government on sport diplomacy and their Sport Horizon strategy, using the Games to strengthen regional partnerships and boost Australia's international sporting presence
Drive proactive engagement with Ministers, Parliamentarians, advisers and Federal Departments to coordinate and progress critical policy and delivery enablers (e.g. workplace relations, immigration, biosecurity, transport and security), with regular presence in Canberra
Provide strategic advice on legislative and regulatory pathways required to enable Games delivery, ensuring early identification of risks, opportunities and required reforms
Work with Paralympics Australia and the Australian Olympic Committee to align and leverage Federal Government support
Advise the Brisbane 2032 President, CEO and members of the Executive and Senior Leadership Teams on Federal Government matters, including preparing detailed briefings, presentations, options papers and similar
Participate in pre-engagement planning and post-engagement reviews to refine strategy and ensure follow-up
Provide support to Brisbane 2032 operational teams to support delivery of interstate and international-facing initiatives that require coordination with Federal agencies, state governments, or international partners

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Technologist, ASIC Development Engineering (RTL Design and SOC)

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