Technologist, ASIC Development Engineering (RTL Design and SOC) Job at Sandisk (Bengaluru)

Technologist, ASIC Development Engineering

We are looking for a highly skilled and experienced individual for SoC PD lead p...

Location

India , Bengaluru

Salary:

Not provided

Sandisk

Expiration Date

Until further notice

Requirements

Bachelor’s or master’s degree in electrical engineering, Computer Engineering, or a related field
A minimum of 13 to 15 years of experience in leading RTL to GDSII implementation effort across various SoCs
Proven ability in technically leading a small/medium-sized team for executing projects preferred
Hands-on experience on the entire PD Flow from RTL to GDSII
Should have a good understanding of Floor planning, Power Planning, Placement & Optimization, CTS, Routing, Design Convergence, and Sign-off with in-depth expertise in at least one of these domains
Working knowledge about OCV, MM/MC optimization and multi-power designs (Level shifters, Isolation cells, etc)
Exposure to static timing analysis fixes including automated ECO generation
Strong in areas on CTS, Power, Bump planning, Floorplan
Experience with tools (e.g., Synopsys FusionCompiler, PrimeTime, Cadence Innovus, Constraints Manager, Redhawk, Calibre etc.) and methodologies
Library preparation in any environment (Synopsys, Cadence, etc)

Job Responsibility

To be responsible for leading RTL-to-GDSII SoC implementation effort
To collaborate with cross-functional teams, including Design, Verification, Analog, DFT, SIPI etc.
To develop and guide the team members in their work, enhancing their technical capabilities and increasing productivity
To ensure process compliance during project execution and enable / participate in technical discussions/reviews
To prepare and submit status reports for minimizing exposure and risks on the project or closure of escalations
Stay abreast of industry trends and emerging technologies in related fields, and incorporate best practices into the team’s workflow
Foster a culture of innovation, collaboration, and continuous improvement

Fulltime

Technologist, ASIC Development Engineering (RTL Design and SoC architecture, Lint)

Are you ready to push the boundaries of what's possible in technology? Join the ...

Location

India , Bengaluru

Salary:

Not provided

Sandisk

Expiration Date

Until further notice

Requirements

Bachelor’s or master’s degree in electrical engineering, Computer Engineering, or a related field with 14-18 years of experience
Proven experience in ASIC RTL design, with a strong grasp of Verilog/System Verilog
Strong understanding of SoC architecture, AMBA protocols (AXI/AHB/APB), interconnects and peripherals for debug
Prior knowledge of Power Intent format (UPF) and Timing Constraints (SDC) is a must
Proficiency in scripting languages (e.g., Python, TCL) for automation
Hands-on with EDA tools (simulation, lint, CDC, synthesis, formal verification)
Strong problem-solving skills and the ability to thrive in a dynamic environment
Excellent communication and teamwork abilities

Job Responsibility

Innovate, implement, and verify RTL code for complex ASICs
Own SoC subsystems related to CPU complex, DDR, Host, Flash, Debug, Clocks, resets, Power domains etc. for top of the line flash controllers
Ensure robust design methodologies including Lint, CDC, RDC, CLP and FC-Elab
Utilize advanced AI-driven tools, including GitHub Copilot, to streamline the design process
Collaborate with DFT, PD, Hardware and Firmware teams for delivering the most optimal solution
Lead design reviews and provide mentorship to junior engineers
Work along side with the SoC Managers and SoC Leads to deliver best-in-class solution
Stay abreast of the latest industry trends and emerging technologies in AI and ASIC design

Fulltime

Technologist, ASIC Development Engineering

Are you ready to push the boundaries of what's possible in technology? Join the ...

Location

India , Bengaluru

Salary:

Not provided

Sandisk

Expiration Date

Until further notice

Requirements

Bachelor’s or master’s degree in electrical engineering, Computer Engineering, or a related field with 14-18 years of experience
Proven experience in ASIC RTL design, with a strong grasp of Verilog/System Verilog
Strong understanding of SoC architecture, AMBA protocols (AXI/AHB/APB), interconnects and peripherals for debug
Prior knowledge of Power Intent format (UPF) and Timing Constraints (SDC) is a must
Proficiency in scripting languages (e.g., Python, TCL) for automation
Hands-on with EDA tools (simulation, lint, CDC, synthesis, formal verification)
Strong problem-solving skills and the ability to thrive in a dynamic environment
Excellent communication and teamwork abilities

Job Responsibility

Innovate, implement, and verify RTL code for complex ASICs
Own SoC subsystems related to CPU complex, DDR, Host, Flash, Debug, Clocks, resets, Power domains etc. for top of the line flash controllers
Ensure robust design methodologies including Lint, CDC, RDC, CLP and FC-Elab
Utilize advanced AI-driven tools, including GitHub Copilot, to streamline the design process
Collaborate with DFT, PD, Hardware and Firmware teams for delivering the most optimal solution
Lead design reviews and provide mentorship to junior engineers
Work along side with the SoC Managers and SoC Leads to deliver best-in-class solution
Stay abreast of the latest industry trends and emerging technologies in AI and ASIC design

Fulltime

Technologist, ASIC Development Engineering

We are looking for a highly skilled and experienced individual for SoC PD lead p...

Location

India , Bengaluru

Salary:

Not provided

Sandisk

Expiration Date

Until further notice

Requirements

Bachelor’s or master’s degree in electrical engineering, Computer Engineering, or a related field
A minimum of 13 to 15 years of experience in leading RTL to GDSII implementation effort across various SoCs
Proven ability in technically leading a small/medium-sized team for executing projects preferred
Hands-on experience on the entire PD Flow from RTL to GDSII
Should have a good understanding of Floor planning, Power Planning, Placement & Optimization, CTS, Routing, Design Convergence, and Sign-off with in-depth expertise in at least one of these domains
Working knowledge about OCV, MM/MC optimization and multi-power designs (Level shifters, Isolation cells, etc)
Exposure to static timing analysis fixes including automated ECO generation
Strong in areas on CTS, Power, Bump planning, Floorplan
Experience with tools (e.g., Synopsys FusionCompiler, PrimeTime, Cadence Innovus, Constraints Manager, Redhawk, Calibre etc.) and methodologies
Library preparation in any environment (Synopsys, Cadence, etc)

Job Responsibility

To be responsible for leading RTL-to-GDSII SoC implementation effort
To collaborate with cross-functional teams, including Design, Verification, Analog, DFT, SIPI etc
To develop and guide the team members in their work, enhancing their technical capabilities and increasing productivity
To ensure process compliance during project execution and enable / participate in technical discussions/reviews
To prepare and submit status reports for minimizing exposure and risks on the project or closure of escalations
Stay abreast of industry trends and emerging technologies in related fields, and incorporate best practices into the team’s workflow
Foster a culture of innovation, collaboration, and continuous improvement

Fulltime

Technologist, ASIC Development Engineering

We are looking for a highly skilled and experienced individual for SoC PD lead p...

Location

India , Bengaluru

Salary:

Not provided

Sandisk

Expiration Date

Until further notice

Requirements

Bachelor’s or master’s degree in electrical engineering, Computer Engineering, or a related field
A minimum of 13 to 15 years of experience in leading RTL to GDSII implementation effort across various SoCs
Proven ability in technically leading a small/medium-sized team for executing projects preferred
Hands-on experience on the entire PD Flow from RTL to GDSII
Should have a good understanding of Floor planning, Power Planning, Placement & Optimization, CTS, Routing, Design Convergence, and Sign-off with in-depth expertise in at least one of these domains
Working knowledge about OCV, MM/MC optimization and multi-power designs (Level shifters, Isolation cells, etc)
Exposure to static timing analysis fixes including automated ECO generation
Strong in areas on CTS, Power, Bump planning, Floorplan
Experience with tools (e.g., Synopsys FusionCompiler, PrimeTime, Cadence Innovus, Constraints Manager, Redhawk, Calibre etc.) and methodologies
Library preparation in any environment (Synopsys, Cadence, etc)

Job Responsibility

To be responsible for leading RTL-to-GDSII SoC implementation effort
To collaborate with cross-functional teams, including Design, Verification, Analog, DFT, SIPI etc
To develop and guide the team members in their work, enhancing their technical capabilities and increasing productivity
To ensure process compliance during project execution and enable / participate in technical discussions/reviews
To prepare and submit status reports for minimizing exposure and risks on the project or closure of escalations
Stay abreast of industry trends and emerging technologies in related fields, and incorporate best practices into the team’s workflow
Foster a culture of innovation, collaboration, and continuous improvement

Fulltime

Technologist, ASIC Development Engineering (PD Methodology & CAD Flow Architect/Lead)

Sandisk’s ASIC team builds state-of-the-art memory controllers that power world-...

Location

India , Bengaluru

Salary:

Not provided

Sandisk

Expiration Date

Until further notice

Requirements

10+ years of experience in Physical Design, PD Methodology, or CAD for advanced ASICs
Deep, hands-on understanding of complete PD flow, including: Synthesis, Logical Equivalence Checking (LEC), DFT insertion and integration, Place & Route, Static Timing Analysis (STA), Physical Verification, EM/IR analysis
Strong grasp of inter-dependencies across the PD flow and their impact on design convergence and PPA
Proven experience architecting PD methodologies and flows for complex SoCs or IPs on advanced nodes
M.Tech in VLSI Design or a related field (or equivalent industry experience)
Proficiency in scripting and automation using TCL, Perl, and/or Python
Experience working in multi-project, high-complexity environments with tight schedules

Job Responsibility

Lead and mentor the PD Methodology/CAD team to deliver scalable, production-ready flows and innovative solutions across multiple programs
Design and architect end-to-end PD methodologies (RTL to GDS) for advanced technology nodes, ensuring correctness, robustness, and scalability
Drive continuous improvement in PPA (Power, Performance, Area) and turnaround time through flow optimization, automation, and best practices
Work closely with foundry partners to understand node-specific challenges (design rules, variability, EM/IR, signoff requirements) and develop correct-by-construction solutions
Collaborate with IP teams, RTL design, DFT, and signoff teams to address cross-domain optimization challenges and enable smooth design convergence
Develop “shift-left” and “push-up” methodologies to detect and resolve issues early in the design cycle, improving predictability and schedules
Deliver high-quality, signoff-clean flows with strong emphasis on reliability, yield, and manufacturability
Leverage AI/ML techniques to improve quality, debug efficiency, predict design issues, and enhance overall productivity
Foster a culture of technical excellence and innovation, encouraging the team to develop novel solutions for next-generation challenges

Fulltime

Technologist, ASIC Development Engineering (PD Methodology & CAD Flow Architect/Lead)

Sandisk’s ASIC team builds state-of-the-art memory controllers that power world-...

Location

India , Bengaluru

Salary:

Not provided

Sandisk

Expiration Date

Until further notice

Requirements

10+ years of experience in Physical Design, PD Methodology, or CAD for advanced ASICs
Deep, hands-on understanding of complete PD flow, including: Synthesis, Logical Equivalence Checking (LEC), DFT insertion and integration, Place & Route, Static Timing Analysis (STA), Physical Verification, EM/IR analysis
Strong grasp of inter-dependencies across the PD flow and their impact on design convergence and PPA
Proven experience architecting PD methodologies and flows for complex SoCs or IPs on advanced nodes
M.Tech in VLSI Design or a related field (or equivalent industry experience)
Proficiency in scripting and automation using TCL, Perl, and/or Python
Experience working in multi-project, high-complexity environments with tight schedules

Job Responsibility

Lead and mentor the PD Methodology/CAD team to deliver scalable, production-ready flows and innovative solutions across multiple programs
Design and architect end-to-end PD methodologies (RTL to GDS) for advanced technology nodes, ensuring correctness, robustness, and scalability
Drive continuous improvement in PPA (Power, Performance, Area) and turnaround time through flow optimization, automation, and best practices
Work closely with foundry partners to understand node-specific challenges (design rules, variability, EM/IR, signoff requirements) and develop correct-by-construction solutions
Collaborate with IP teams, RTL design, DFT, and signoff teams to address cross-domain optimization challenges and enable smooth design convergence
Develop “shift-left” and “push-up” methodologies to detect and resolve issues early in the design cycle, improving predictability and schedules
Deliver high-quality, signoff-clean flows with strong emphasis on reliability, yield, and manufacturability
Leverage AI/ML techniques to improve quality, debug efficiency, predict design issues, and enhance overall productivity
Foster a culture of technical excellence and innovation, encouraging the team to develop novel solutions for next-generation challenges

Fulltime

New

Precast Concrete Pourer

We’re recruiting an experienced Concrete Pourer to join our production team. In ...

Location

United Kingdom , Skelmersdale

Salary:

Not provided

JRL Group

Expiration Date

Until further notice

Requirements

Previous experience in concrete pouring, precast manufacturing, or related roles within an industrial environment
Good understanding of concrete behaviour and pour scheduling
Strong attention to detail and quality focus
Ability to work as part of a team and follow direction from supervisors
A proactive attitude to health & safety
CSCS or equivalent certification (desirable)

Job Responsibility

Prepare and ensure moulds are ready for casting in line with production schedules
Pour concrete accurately and efficiently into forms/shuttering
Work with production and machine teams to coordinate pour operations and target output
Monitor concrete placement to ensure quality finish and integrity
Maintain a clean, organised and safe working area in compliance with health & safety protocols
Report any issues or non conforming products to supervisors promptly

What we offer

Competitive pay and benefits package
Stable, full time employment within a well established company
Opportunity for training and career progression within the JRL Group
On site facilities and supportive team environment

Fulltime

Technologist, ASIC Development Engineering (RTL Design and SOC)

Sandisk

Location:
India , Bengaluru

Category:
IT - Software Development

Contract Type:
Not provided

Salary:

Job Description:

Job Responsibility:

Requirements:

Nice to have:

Additional Information:

Job Posted:
January 11, 2026

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Technologist, ASIC Development Engineering (RTL Design and SOC)

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Salary:

Job Description:

Job Responsibility:

Requirements:

Nice to have:

Additional Information:

Job Posted:January 11, 2026

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