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Join the Silicon One Team at Cisco, a group at the forefront of developing Cisco's groundbreaking silicon architecture. We are a collaborative unit focused on pushing the boundaries of ASIC design for advanced process nodes. As part of our team, you will contribute to defining innovative Physical Design methodologies and creating robust flows essential for developing our complex chips. You will also have the opportunity to work hands-on with the Physical Design of intricate chip partitions.
Job Responsibility:
Developing timing constraints at block, sub-chip, and full-chip levels in test modes, performing quality checks such as duplicated constraints, promotion/demotion between block and top level SDCs
Check timing for unconstrained endpoints, no clock, etc
Your role may include SDC validation, CDC delay check, and SDC flow development
Developing methodologies, guidelines, and checklists to streamline STA work, resolve design and flow issues, and drive execution to ensure progress and accuracy
Requirements:
Bachelor’s degree in electrical or computer engineering (or other equivalent field) with 8+ years of related work experience
Experience with block/full chip SDC development in test modes (scan shift, scan capture, atpg capture modes)
Expertise in Static Timing Analysis and prior working experience with STA tools like PrimeTime
Programming skills in at least 2 or more of the following languages: Perl, TCL, Python, Makefile, or other relative scripting languages
Nice to have:
Master’s degree in electrical or computer engineering (or other equivalent field) with 6+ years of related work experience
Background in debugging and analyzing timing constraints, timing closure of DFT modes such as scan shift/capture and BIST
Prior working experience with SDC debugging & STA tools: Synopsys GCA/TCM/Primetime
Prior working experience with synthesis tools: Synopsys Fusion Compiler
Prior working experience with Tessent tool: DFT insertion in RTL