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Processor silicon DDR interface feature enable, electrical test and debug engineer. In this role, this senior level engineer will be part of a highly technical team that develops test plans, executes bring-up & feature enable, & debugs electrical issues in the memory sub-system of new processors.
Job Responsibility:
Provides DDR technical leadership in the development of new test & validation features
Closely interacts with silicon design (DRAM controller and memory Phy) in test execution & debug, as well as in feature definition for future product generation
Writes comprehensive electrical & functional test plans for the memory validation of processors
Executes electrical & functional test plans for AMD processors using hardware & software validation tools, oscilloscopes, & logic analyzers
Debug of electrical & functional issues of the memory sub-system of new processors
Provides detailed input into the platform definition & review of platform designs used in the silicon validation of new processors
Requirements:
Requires experience and demonstrated technical expertise in the development & execution of platform level electrical & functional test plans
Requires extensive hands-on experience and demonstrated technical expertise in the debug of I/O interfaces such as DDR
Familiar with DDR signal measurement, reading schematics and layout documentation
Requires good written and oral communication skills
Familiar with Python, Ruby, Perl language
Bachelor with 6+ years’ experience
Master with 3+ years’ experiences
Nice to have:
DDR5(4)/LPDDR5(4) Memory test experience on electronic components such as uProcessors
Working knowledge of lab equipment such as oscilloscopes, logic analyzers and protocol analyzers
Self-organizing and the ability multitask based on priorities
Scripting and automation tool development
Linux environment validation or development experience