Synthesis Pd Lead Job at AMD (Karnataka)

Rtl Synthesis And Constraints Lead

The focus of this role is to plan, build, and execute the verification of new an...

Location

India , Hyderabad

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

7-10 years of experience
Proven experience in SOC timing lead role with focus on Timing closure of subsystem IP and delivery to SOC to PD teams
Expertise and strong understanding of RTL quality checks and constraints debug for Subsystem IP
Excellent communication skill
Strong analytical and problem-solving abilities, including designing experiments for performance
Self-motivated and proactive in driving initiatives
Bachelor's or Master's degree in Computer Engineering or Electrical Engineering

Job Responsibility

Develop timing constraints for Subsystem for SOC
Work with RTL leads and use or define best practices for constraint development
Collaborate with Physical design and DFT constraints team members for timing sign-off
Ensure timely delivery of projects while meeting quality standards
Provide strong technical solution to internal and external stakeholders

Fulltime

Pmts Silicon Design Engineer

WHAT YOU DO AT AMD CHANGES EVERYTHING. At AMD, our mission is to build great pro...

Location

India , Hyderabad

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

14–18+ years of semiconductor design experience
Strong hands‑on RTL design and microarchitecture ownership, with designs that progressed through PD and tapeout
Direct experience working within or closely alongside Physical Design teams
Deep understanding of SDC intent, timing, clocking, partitioning, and physical closure trade‑offs
Proven ability to resolve PD issues through architectural and RTL‑level solutions, not late physical workarounds
Experience driving or contributing to shift‑left initiatives or early physical feasibility analysis
Comfort operating as a senior technical authority, making cross‑domain engineering decisions
Exposure to AI‑assisted or highly automated design flows is a strong plus
Own creation and maintenance of physical‑aware RTL to enable PNR hierarchy, including partitioning, feedthroughs, repeaters, and physical intent insertion
Partner with SOC Design to translate logical IP integration into physical‑aware RTL and with IP design team creation digital‑on‑top RTL wrappers for analog IPs

Job Responsibility

Own Physical Design shift‑left strategy, ensuring PD risks are identified at RTL, SDC, and paper‑floorplan stages
Act as chief engineering authority for AI‑assisted and automated PD execution, defining where AI can act autonomously and where human judgment is required
Bridge RTL, microarchitecture, and PD, translating early PD findings into architectural and RTL‑level corrective actions
Define and enforce PD readiness and quality bars across synthesis, PnR, STA, and physical closure
Lead predictive closure and risk management, using early indicators to forecast timing, ECO churn, and execution complexity
Govern signoff readiness, ensuring AI‑augmented flows never compromise correctness or confidence
Codify execution playbooks and best practices to reduce variability and scale high‑quality PD execution across teams
Serve as a trusted technical peer to RTL architects, PD leads, and AI/methodology owners

Fulltime

Principal Silicon Engineer

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the...

Location

United States , Mountain View

Salary:

139900.00 - 274800.00 USD / Year

Microsoft Corporation

Expiration Date

Until further notice

Requirements

Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience OR equivalent experience
Ability to meet Microsoft, customer and/or government security screening requirements
Ability to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter
Provide proof of country of citizenship or proof of US residency or other protected status for export control assessment
Bachelor of Science in Electrical or Computer Engineering
8+ years of experience in RTL design and design checks (CDC/RDC/VCLP/LINT)
8+ years of experience in Synthesis, Timing constraints and Power Performance Area (PPA) trade-offs
Proficiency in RTL to Physical Design collateral development including timing and synthesis constraints
Knowledge of full RTL2GDS flow
Hands-on experience with industry tools for synthesis, STA, and PD flows (e.g., PrimeTime, Genus/DC, Innovus/ICC2)

Job Responsibility

Serve as the middle-engineering technical leader at the intersection of RTL, physical design, and mixed-signal integration for Azure’s custom silicon programs
Ensure that design intent—digital and mixed-signal—is captured accurately in constraints, flows, and sign-off methodologies
Lead the capture and validation of design intent for digital and mixed-signal blocks, ensuring accurate constraints and seamless integration across front-end and physical design flows
Provide static timing leadership for mixed-signal interfaces, driving timing closure, exception quality, and correlation across corners
Partner closely with RTL, PD, mixed-signal, DFT, and CAD teams to resolve cross-domain issues and maintain alignment on timing, power, and functional requirements
Run, review and debug physical design flows, timing reports, ensuring consistency with synthesis and STA assumptions and driving convergence through targeted mitigations
Contribute to design automation including leveraging AI, constraint-checking, and flow improvements that enhance execution efficiency and PPA
Operate with limited direction, demonstrating strong ownership, attention to detail, and the ability to communicate clear, data-driven status, risks, and mitigation plans to program leadership

Fulltime

Senior Staff Physical Design Engineer

We are looking for an adaptive, self-motivative physical design engineer to join...

Location

Malaysia , Penang

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

Strong experience and specialization in deep‑submicron ASIC physical design, including all phases from RTL-to-GDSII and signoff
Proven record of Physical Design signoff flow
Hands-on experience with industry-standard EDA tools (e.g., Cadence Innovus, Tempus, PrimeTime, Fusion Compiler, Calibre)
Excellent scripting skills in TCL, Shell, Python, or Perl to enhance PD flows and automation
Proven ability to work with cross-functional teams across multiple sites/time zones
Strong analytical, problem-solving, and communication skills
Familiarity with CPU and or GPU architecture
Proficiency in data analysis and interpretation

Job Responsibility

Static Timing Analysis (STA) across MMMC scenarios: Driving timing closure at block and full‑chip levels, resolving violations through ECOs, constraint refinements, and reviewing SoC and block‑level signoff readiness. Lead timing signoff (setup, hold, OCV, AOCV/POCV, SI, CDC interfaces) across all modes and corners
Logic Equivalence Check (LEC) for all blocks and full‑chip: Executing equivalence verification between RTL, synthesis, and P&R databases
Low‑power structural checks (UPF/CLP): Ensuring correctness of power‑intent implementation, power‑domain crossings, isolation/retention, and coverage of low‑power signoff flows
Physical Integrity Signoff: Overseeing DRC/LVS structural verifications, and ensuring designs adhere to foundry signoff rules. Perform and review IR drop, EM, and power integrity signoff
Clocking and top‑level mesh implementation and signoff
Own and drive block-level and/or full-chip physical implementation and signoff to tape-out
Analyze complex cross-block and top-level signoff issues and define closure strategy
Define and enforce signoff criteria, methodologies, and best practices
Partner with PD implementation teams to guide ECO strategy for timing, power, and physical fixes
Identify risk areas early and proactively drive mitigation plans

Senior SoC/ASIC Physical Design Engineer

About the Job: We are seeking a highly skilled Senior SoC/ASIC Physical Design E...

Location

United States , Irvine

Salary:

Not provided

Xcelerium

Expiration Date

Until further notice

Requirements

Bachelor’s degree in Electrical Engineering, Computer Engineering, or Computer Science (Master’s preferred)
10+ years of experience in ASIC/SoC physical design and flow development
Expertise in RTL-to-GDSII physical design and signoff flows
Strong experience with Synopsys EDA tools, understanding tool capabilities and underlying algorithms
Proficient in physical design methodologies: synthesis, place & route, STA, formal verification, CDC, and power analysis
Knowledge of FinFET and deep sub-micron CMOS technologies, including power dissipation, leakage, and dynamic behavior
Familiarity with DFT, Scan, MBIST, and LBIST methodologies and their impact on physical design
Proficient in scripting languages (Python, Tcl, Perl, bash/csh) and automation using Makefiles
Skilled in extraction and analysis of design parameters, QOR metrics, and implementing voltage scaling (SVS, DVFS) and SRAM split rail architectures
Proven ability to work collaboratively in dynamic environments, lead design closure activities, and drive execution with a proactive, solution-oriented mindset

Job Responsibility

Develop and Implement PD Flow: Establish a modern physical design (PD) flow utilizing the latest EDA tool fusion and machine learning (ML) techniques to maximize PPA efficiency, optimize resource allocation, and achieve industry-leading time-to-closure and tapeout
End-to-End Physical Design Execution: Perform partition synthesis and physical implementation, including synthesis, floorplanning, power/ground grid generation, place & route, timing, noise, physical verification, electromigration, voltage drop, and signoff checks
Methodology and Automation: Create and refine physical design methodologies and automation scripts to streamline implementation and signoff processes
Cross-Functional Collaboration: Work closely with RTL, DFT, and ASIC design teams to define architectural feasibility, establish timing, power, and area targets, and explore design trade-offs
Drive Design Closure: Utilize an objective, metrics-driven approach to resolve design, timing, and flow issues and ensure predictability in achieving project milestones
Signoff Ownership: Lead signoff closure activities, including static timing analysis (STA), noise analysis, logic equivalency, physical verification, and power integrity (EM/IR)

What we offer

We provide competitive compensation package

Principal Physical Design Engineer

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the...

Location

India , Bangalore

Salary:

Not provided

Microsoft Corporation

Expiration Date

Until further notice

Requirements

Bachelor's or master’s in electrical or computer engineering or related field with 12+ years of experience
Experience in physical design implementation, signoff at block / sub system / sub-chip / SoC level
Experience in tapeouts of complex ASICs in leading edge technology
Experience in leading team to deliver planned PD goals
Ability to meet Microsoft, customer and/or government security screening requirements are required for this role
These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter

Job Responsibility

Physical Design tasks at block, subsystem, sub-chip, and/or full-chip level
Floorplanning, Synthesis, Placement, CTS and custom clocking, Routing, Static Timing, Physical Verification, Formal Equivalency, Power Efficiency, IR-Drop, and EM
Physical Design flow development/automation and evaluation of and recommendations for technology, IP, and vendor selection
Drive PD team at block/Sub System / Sub Chip / SOC level to set and deliver quality results as per planned milestone goals
Work with limited direction, have keen attention to detail, and be able to provide crisp status of progress, issues, and risks on the program to the management team

Fulltime

Principal Physical Design Engineer

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the...

Location

United States , Mountain View

Salary:

139900.00 - 274800.00 USD / Year

Microsoft Corporation

Expiration Date

Until further notice

Requirements

Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience
Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience
Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience
equivalent experience
Ability to meet Microsoft, customer and/or government security screening requirements
Experience in physical design implementation, signoff at block / sub system / sub-chip / SoC level
Experience in tapeouts of complex ASICs in leading edge technology
Experience in leading team to deliver planned PD goals

Job Responsibility

Lead and execute Physical Design activities at block, sub-chip, and full-chip levels
Contribute to Physical Design flow development, automation, and methodology improvements
Evaluate and recommend technology nodes, IP selection, EDA tools, and vendor solutions
Provide clear and concise status updates on progress, risks, and mitigation plans to management
Operate independently with minimal supervision while maintaining strong attention to detail
Support program needs, including occasional travel as required
Drive all phases of implementation including: Floorplanning
Synthesis
Placement and optimization
Clock Tree Synthesis (CTS) and custom clocking

Fulltime

Technologist lead full chip soc sign-off emir closure engineer

The candidate to have a passion for complex processor architecture, digital desi...

Location

India , Bengaluru

Salary:

Not provided

Sandisk

Expiration Date

Until further notice

Requirements

Minimum 8 to 12 years of relevant work experience
Expertise in Synthesis, ICC2/FC (Fusion Compiler) Physical Design flows/methodologies or equivalent tools
Expertise in Signoff tools like Ansys Redhawk/RHSC on EMIR, PT-PX for Power signoff and Primetime for Timing
Should have worked as a go to person or technical lead for at least few full chip projects
Strong technical leadership and ability to mentor/guide/coach design engineers
Strong inter-personal skills and ability to collaborate with teams spread across multiple geos
Should have good scripting experience in Shell, Python, Perl, TCL, UNIX
Must be using AI technologies in day to day problem solving
Bachelors or Masters degree in Electronics and communication engineering/Electronics and Electrical Engineering

Job Responsibility

EMIR closure at Tile /Partition/Subsytem/SOC level on a particular node
Ownership of EMIR Flow & Signoff
Drive EMIR closure for design blocks and full-chip integration
Align EMIR analysis phases with PD milestones (INIT, PREFINAL, FINAL)
Ensure compliance with signoff limits provided by SIPI team for given technology node
Ability to analyze EMIR violations and propose implementation choices
Familiarity with DFx and scan architecture for EMIR considerations
Define EMIR signoff strategy, including IR drop and electromigration analysis
Review floorplan, clocking, and bus structures for IR hotspots
Coordinate bump allocation and power rail alignment with integration teams

Fulltime

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Synthesis Pd Lead

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