Study of a hybrid DRAM memory using ferroelectric technology

This thesis is set in the context of emerging hybrid memories that combine volatile and persistent regions within the same memory subsystem. Thanks to recent progress in CMOS-compatible ferroelectric materials, it is now possible to envision high-density architectures suited to normally-off / instant-on embedded systems. The scientific challenge is to understand how to use these memories efficiently to improve performance, energy consumption, and wake-up time. The proposed work will study the memory behavior of representative workloads such as embedded AI and signal processing, in order to identify which data should remain in volatile memory and which can be stored persistently. Special attention will be given to access latency, energy cost, and cell endurance. The thesis will also aim to design data management algorithms capable of dynamically migrating cold and hot data between memory regions. The final goal is to propose a management strategy integrated into the memory controller, in interaction with the operating system and firmware, to simplify standby modes and optimize overall system behavior. Expected outcomes include a workload characterization methodology, rules for volatile/persistent partitioning, and a controller architecture implemented as a finite-state machine. The thesis should also quantify the gains in execution time, energy consumption, and controller hardware cost.