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We are looking for an experienced Verification Engineer to join our team for cutting-edge server memory products. This individual will be responsible for driving the verification efforts of DDR interfaces, including advanced memory protocols such as DFI, DDR5, and LPDDR5/LPDDR6, across a range of DIMMs (Dual In-line Memory Modules). The ideal candidate will possess advanced knowledge of SystemVerilog, UVM, C/C++, and scripting languages like Python/Perl.
Job Responsibility:
Work with a team verification engineers in the development and execution of verification plan for DDR5, LPDDR5, and DFI memory systems in server products
Comprehend the PHY's interaction in the complete system which includes HW (Silicon), FW, BIOS & SW and ensure that FW, BIOS & SW are aligned to enable all features of the memory interface
Understand RTL and micro-architecture sufficiently to engage in cross functional discussions with IP/Domain architects and Design engineers for planning and debug
Knowledge sharing and other contributions to verification methodology
Support Post-Si teams for Product Performance, Power and functional issues debug/resolution
Requirements:
Bachelor's or Master's degree in related discipline
Advanced knowledge of SystemVerilog, UVM, C/C++, and scripting languages like Python/Perl
Developed and implemented SystemVerilog and UVM based testbenches, simulation environments, and functional coverage models for DDR5 and LPDDR5 systems
Worked closely with hardware, firmware, and software teams to align on system-level memory architecture, identify potential integration issues, and define validation requirements early in the design phase
Built VIPs and BFMs for memory interfaces from scratch (preferrable)
GLS, NLP, XPROP simulation experience is preferable
Strong proficiency in system verilog assertions, constraints and coverage
Worked in formal verification methods, with proven record of tool usage beyond the standard apps
Excellent communication, management, and presentation skills
Nice to have:
Built VIPs and BFMs for memory interfaces from scratch