Staff/ Sr Staff RTL Design Engineer Job at Synopsis Engineering (Bengaluru)

Job Description

Synopsys software engineers are key enablers in the world of Electronic Design Automation (EDA), developing and maintaining software used in chip design, verification and manufacturing. They work on assignments like designing, developing, and troubleshooting software, leveraging the state-of-the-art technologies like AI/ML, GenAI and Cloud. Their critical contributions enable world-wide EDA designers to extend the frontiers of semiconductors and chip development.

Job Responsibility

Developing and modeling RTL logic in Verilog for embedded memory test and SLM IP blocks
Performing digital design validation and functional verification at both block and SoC levels
Executing logic synthesis, static timing analysis, and generating fault coverage reports to ensure robust designs
Applying DFT (Design-for-Test) expertise for comprehensive memory and logic testing
Identifying and troubleshooting design timing and DFT functional issues to optimize chip performance
Utilizing and scripting in languages such as Tcl to automate design and verification workflows
Defining architecture, logic, test bench designs, and embedded software functions for advanced test and analytics
Developing and maintaining technical collateral including test suites, protocol documentation, and debug guides
Collaborating with R&D and marketing teams to define new features, drive enhancements, and align product roadmaps
Delivering product training, managing customer support cases, and ensuring turnaround time (TAT) metrics are met or exceeded

Requirements

3-5 years of relevant experience in ASIC digital design and verification
Proficiency in RTL simulation, logic synthesis, and timing verification tools
Deep expertise in UVM, SystemVerilog, and protocol verification (e.g., IEEE1500, IEEE1687, AXI, AMBA)
Hands-on experience with VIPs and transactors in simulation and emulation environments
Strong understanding of DFT architectures, interconnects, and cache coherency protocols
Familiarity with debug tools such as Verdi and workflows for performance analysis
Programming skills in SystemVerilog, UVM, Verilog, C/C++, Python, and scripting languages like Tcl
Experience with EDA tools such as VCS, Verdi, and DC, and methodologies including VC Auto-Testbench and protocol compliance checking

Nice to have

Analytical thinker with exceptional problem-solving skills
Effective communicator, able to collaborate across disciplines and with external partners
Proactive, self-motivated, and adaptable in fast-paced environments
Committed to quality, detail, and continuous learning
Team player who values diversity, inclusion, and mentorship
Customer-focused, dedicated to delivering timely and effective solutions

What we offer

Comprehensive medical and healthcare plans that work for you and your family
In addition to company holidays, we have ETO and FTO Programs
Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more
Purchase Synopsys common stock at a 15% discount, with a 24 month look-back
Save for your future with our retirement plans that vary by region and country
Competitive salaries

Synopsis Engineering - All Job Offers

Select Country

Staff/ Sr Staff RTL Design Engineer

Job Description

Job Responsibility

Requirements

Nice to have

What we offer

Looking for more opportunities?

Staff/ Sr Staff RTL Design Engineer

Asic Engineer Sr Staff

Electrician

Electrician

Electrician - Industrial

Field Service Engineer 2

Business Operations Analyst 4

Business Operations Analyst 1

Entry-Level Production

Our AI answers in your language