Staff Silicon Design Engineer (Physical Design) Job at AMD (Penang)

Senior Staff Physical Design Engineer

We are looking for an adaptive, self-motivative physical design engineer to join...

Location

Malaysia , Penang

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

Strong experience and specialization in deep‑submicron ASIC physical design, including all phases from RTL-to-GDSII and signoff
Proven record of Physical Design signoff flow
Hands-on experience with industry-standard EDA tools (e.g., Cadence Innovus, Tempus, PrimeTime, Fusion Compiler, Calibre)
Excellent scripting skills in TCL, Shell, Python, or Perl to enhance PD flows and automation
Proven ability to work with cross-functional teams across multiple sites/time zones
Strong analytical, problem-solving, and communication skills
Familiarity with CPU and or GPU architecture
Proficiency in data analysis and interpretation

Job Responsibility

Static Timing Analysis (STA) across MMMC scenarios: Driving timing closure at block and full‑chip levels, resolving violations through ECOs, constraint refinements, and reviewing SoC and block‑level signoff readiness. Lead timing signoff (setup, hold, OCV, AOCV/POCV, SI, CDC interfaces) across all modes and corners
Logic Equivalence Check (LEC) for all blocks and full‑chip: Executing equivalence verification between RTL, synthesis, and P&R databases
Low‑power structural checks (UPF/CLP): Ensuring correctness of power‑intent implementation, power‑domain crossings, isolation/retention, and coverage of low‑power signoff flows
Physical Integrity Signoff: Overseeing DRC/LVS structural verifications, and ensuring designs adhere to foundry signoff rules. Perform and review IR drop, EM, and power integrity signoff
Clocking and top‑level mesh implementation and signoff
Own and drive block-level and/or full-chip physical implementation and signoff to tape-out
Analyze complex cross-block and top-level signoff issues and define closure strategy
Define and enforce signoff criteria, methodologies, and best practices
Partner with PD implementation teams to guide ECO strategy for timing, power, and physical fixes
Identify risk areas early and proactively drive mitigation plans

Senior Staff Senior Silicon Design Automation Engineer

As a design engineer in our CAD and methodology team, you will be responsible fo...

Location

Malaysia , Penang

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

TCL, Python, PERL, or other scripting languages
PDK, technology enablement
Simulation environments for Spice, PVT
Virtuoso based custom Layout tools and flows
Calibre extraction flows, Totem & Redhawk for EM/IR
SiliconSmart, PrimeTimePhysical aspect of VLSI designs
Strong written and verbal communication skills
Bachelors or Masters degree in computer engineering/Electrical Engineering

Job Responsibility

Execute in CAD infrastructure team supporting multiple IC design projects
Establish and maintain standardized design flows and methodologies
Implement and support customized CAD flows for Fabric design groups
Enable the team in meeting the design and development targets by working closely with external tool vendors
Develop tools flows methodologies on digital back-end domains, sign-off flows for timing, power, EM/IR, DRC/LVS/DFM, etc.
Improve engineering efficiency while improving design quality in IP release process
Be single point contact for bugs and issues for custom and analog physical design team
Build flow in TCL, Python to ensure quality and faster executions
Understand different methodologies used across industry to adopt best practices
Leverage and deploy AMD AI systems to design teams

Fulltime

Analog Design, Staff Engineer

In this role, you will work on the design, development, and refinement of Multi-...

Location

Canada , Ottawa

Salary:

Not provided

Synopsis Engineering

Expiration Date

Until further notice

Requirements

Ph.D., M.Sc. with 3+ years, or B.Sc. with 5+ years of practical analog IC design experience
degree in Electrical Engineering or Computer Engineering or other relevant field of study
In depth familiarity with transistor level circuit design - sound CMOS design fundamentals
Detailed design experience with one, and familiarity with several other SERDES sub-circuits: receive equalizers, samplers, voltage/current-mode drivers, serializers, deserializers, voltage-controlled oscillator, phase mixer, delay-locked loop, phase locked loop, bandgap reference, ADC, DAC
Familiarity with custom digital design (i.e. high-speed logic paths)
Experience with analog/digital interactions for optimizing circuit performance (calibration, adaptation, timing-handoff, etc)
Understanding of design for reliability (i.e. EM, IR, aging, etc.) and layout effects (i.e. matching, reliability, proximity effects, etc.) as well as ESD issues (i.e. circuit techniques, layout)
Experience with tools for schematic entry, physical layout, and design verification
Understanding of SPICE simulators and simulation methods
Knowledgeable in Verilog-A for analog behavioral modeling and simulation-control/data-capture

Job Responsibility

Review SERDES standards to develop novel transceiver architectures and sub-block specifications
Investigate and develop circuit architectures that address architectural bottlenecks and lead to revolutionary improvements in power, area, and performance targets
Oversee physical layout to minimize the effect of parasitics, device stress, and process variation
Present and review simulation data from internal project teams
Document design features and test plans
Consult on the overall electrical characterization of the SERDES IP product. Review customer silicon data for design enhancements. Propose solutions for post-silicon design updates

What we offer

Comprehensive medical and healthcare plans
Time Away in addition to company holidays, ETO and FTO Programs
Family Support including maternity and paternity leave, parenting resources, adoption and surrogacy assistance
ESPP - Purchase Synopsys common stock at a 15% discount
Retirement Plans
Competitive salaries

Fulltime

Staff Analog Design Engineer

Our Hardware Engineers at Synopsys are responsible for designing and developing ...

Location

India , Hyderabad

Salary:

Not provided

Synopsis Engineering

Expiration Date

Until further notice

Requirements

MTech/MS with 4+ years or BTech/BS with 5+ years of practical analog IC design experience in Electrical or Computer Engineering (or related field)
Proven expertise with FinFET technologies and CMOS tape-outs
Deep understanding of Multi-Gbps high-speed designs (PAM4, NRZ) and SERDES architectures
Extensive design experience with SERDES sub-circuits (e.g., TX, RX, adaptive equalizers, PLL, DLL, BGR, regulators, oscillators, ADC/DAC)
Skilled in analog/digital co-design, calibration, adaptation, and timing handoff for optimized circuit performance
Familiarity with ESD protection, custom digital design, and design for reliability (EM, IR, aging, self-heating)
Proficient with schematic entry, physical layout, design verification tools, and SPICE simulators
Experience with scripting languages (TCL, PERL, MATLAB) for post-processing simulation results
Understanding of system-level budgeting (jitter, amplitude, noise) and signal integrity (packaging, parasitics, crosstalk)
Excellent communication and documentation skills

Job Responsibility

Reviewing SerDes standards to develop novel transceiver architectures and detailed sub-block specifications
Investigating and architecting circuit solutions that address performance bottlenecks, enabling significant improvements in power, area, and speed
Collaborating with cross-functional analog and digital design teams to streamline design and verification processes for optimal efficiency and quality
Overseeing and guiding the physical layout to minimize parasitics, device stress, and process variations, ensuring robust silicon performance
Presenting and reviewing simulation data with internal teams and external stakeholders, including industry panels and customer reviews
Documenting design features, test plans, and results, and consulting on electrical characterization and post-silicon analysis for product enhancements
Analyzing customer silicon data to identify design improvement opportunities and proposing solutions for post-silicon updates

What we offer

Comprehensive medical and healthcare plans that work for you and your family
Time Away: In addition to company holidays, we have ETO and FTO Programs
Family Support: Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more
ESPP: Purchase Synopsys common stock at a 15% discount, with a 24 month look-back
Retirement Plans: Save for your future with our retirement plans that vary by region and country
Competitive salaries

Fulltime

Principal Quantum Design Verification Engineer

At Microsoft Quantum, we aim to empower science and scientists to solve the worl...

Location

United States , Redmond

Salary:

139900.00 - 274800.00 USD / Year

Microsoft Corporation

Expiration Date

Until further notice

Requirements

Doctorate in Physics, Engineering, or related field AND 3+ years experience in industry or in a research and development environment
OR Master's Degree in Physics, Engineering, or related field AND 6+ years experience in industry or in a research and development environment
OR Bachelor's Degree in Physics, Engineering, or related field AND 8+ years experience in industry or in a research and development environment
OR equivalent experience
Ability to meet Microsoft, customer and/or government security screening requirements
Microsoft Cloud Background Check
Citizenship & Citizenship Verification
Ability to leverage AI tools to drive innovation and efficiency
Ability to work in an 'AI-first' environment using modern AI tools to accelerate discovery through hardware development

Job Responsibility

Own verification environments and tests for IP and SoC designs, and validate designs in simulation with both pre- and post-layout Register-Transfer Level (RTL) and netlists
Coordinate the execution of contingent staff and external vendors to ensure verification deliverables meet specification and schedule
Set up and manage databases and flows for SoC and IP repositories
set up bug-tracking systems and log, track, manage, and close bugs and issues
drive milestone reviews and status reports
Create test plans for pre-silicon simulation verification across both digital and analog components, including the development of Analog Mixed-Signal (AMS) simulation models
Collaborate with the Design For Test (DFT) team to test DFT features
Align verification methodologies with wider teams and drive continuous improvement to Design Verification processes for at-scale execution
Collaborate effectively with architects, analog mixed-signal designers, verification engineers, and physical design, DFT, and other front-end design teams
Embody our culture and values

Fulltime

Senior Quantum Design Verification Engineer

At Microsoft, our mission is to empower every person and every organization on t...

Location

United States , Redmond

Salary:

119800.00 - 234700.00 USD / Year

Microsoft Corporation

Expiration Date

Until further notice

Requirements

Doctorate in Physics, Engineering, or related field AND 1+ year(s) experience in industry or in a research and development environment, could include completion of a post doctoral research position
OR Master's Degree in Physics, Engineering, or related field AND 4+ years experience in industry or in a research and development environment
OR Bachelor's Degree in Physics, Engineering, or related field AND 6+ years experience in industry or in a research and development environment
OR equivalent experience
Ability to meet Microsoft, customer and/or government security screening requirements
Microsoft Cloud Background Check
proof of citizenship or permanent residency

Job Responsibility

Define pre-silicon Simulation, post-silicon Validation/Characterization plans for SoC/ intellectual property (IP)
coordinate and drive individuals, contingent staff and external vendors towards creating a high-quality design
Own and create verification environments and tests for IP level and SoC level designs
validate designs in simulation with both pre and post layout RTL/netlists
Setup Databases, flows for SoC/IP repositories
Setup Bug-Tracking systems
Drive Milestone reviews, reports/status
Create testplans for pre-silicon simulation verification including for both digital and analog components
performing Analog Mixed Signal Simulation models
Collaborate with Design for Test (DFT) team to test DFT features

Fulltime

Technical Manager URNANO

The candidate will independently perform complex laboratory tasks, including pla...

Location

United States of America , Rochester

Salary:

77216.00 - 115824.00 USD / Year

University of Rochester

Expiration Date

Until further notice

Requirements

Masters degree or higher with major course work in a relevant science or engineering discipline (e.g. microelectronics/optics manufacture, applied physics, physics, chemistry, earth science, mechanical engineering, chemical engineering, biomedical engineering or related academic fields)
Three years of related work experience involving direct assistance to researchers
Three or more years of experience in managing facilities, operations, maintenance, space and equipment in a research or educational setting
Three or more years of experience with the operation and use of electron microscopes and associated sample preparation and characterization
Working knowledge of state-of-the-art scanning electron microscopes (SEM), electron spectroscopy (i.e. EDS), focused ion beam (FIB) preparation of samples, transmission electron microscopy (TEM), physical vapor deposition tools, reactive ion (plasma) processing, wafer scale silicon and associated oxide processing, soft/hard contact lithography and wet chemical processing
Knowledge of Intellectual property law and guidelines is a plus
Ability to design and properly perform all phases of set-up, operation, and repair of complex research and instructional equipment related to electron microscopy instrumentation and ancillary equipment such as specimen preparation equipment
Ability to apply advanced knowledge of principles, concepts and methods related to the laboratory operation, performance
Ability to investigate, devise and help carry out plans for continual renovation and upgrade of equipment and laboratory facilities, including potential new equipment acquisitions to advance the research capabilities of the facility
Ability to develop and perform complex mechanical, electrical, and/or electronic troubleshooting using technical expertise and experience

Job Responsibility

Provides technical operations, directs research and training, and leads efforts to advance highly specialized scientific equipment and facilities within the University of Rochester Integrated Nanosystems Center
Independently perform complex laboratory tasks, including planning and conducting of complete projects of limited scope and or a portion of a larger and more diverse project led by UR PIs
Interface as a primary trainer and mentor for complex laboratory processes for students (undergrad and graduate), faculty, staff and corporate users
Have both classroom and laboratory teaching duties related to microscopy and nanotechnology
Provides engineering services in support of engineering and physical science research activities, encompassing sample characterization, mechanical, electrical, computer, or electronic design, systems analysis, feasibility analysis, instrumentation design, etc., the solution of engineering problems, the development of engineering projects and the supervision of fabrication
Works independently with only occasional suggestions in modifying, varying or adapting standard laboratory procedures to meet special needs of research projects
Performs analyses and scientific data reductions by using standard methods and develops modifications of standard methods to meet special situations
Searches literature for reference to technical problems involved in research projects
writes standard operating procedures (SOPs)
prepares charts, graphs and tables

Fulltime

New

Pharmacy Technician

We’re building a world of health around every individual — shaping a more connec...

Location

United States , Saint Petersburg

Salary:

16.50 - 25.00 USD / Hour

CVS Health

Expiration Date

August 29, 2026

Requirements

Must be at least 16 years of age
Licensure requirements vary by state
Attention and Focus: The ability to concentrate on a task over a period of time without being distracted
Customer Service Orientation: Actively look for ways to help people, and do so in a friendly manner
Notice and understand customers’ reactions, and respond appropriately
Communication Skills: Use and understand verbal and written communication to interact with customers and colleagues
Actively listening by giving full attention to what others are saying, taking time to understand the points being made, asking questions as appropriate, and not interrupting at inappropriate times
Mathematical Reasoning: The ability to use math to solve a problem, such as calculating day’s supply of a prescription
Problem Resolution: Is able to judge when something is wrong or is likely to go wrong
recognizing there is a problem

Job Responsibility

Manage all assigned pharmacy workstations and tasks to support the team’s ability to promptly, safely and accurately fill patient prescriptions all while providing caring service that exceeds customer expectations
Work in an environment where the highest professional and ethical standards are maintained as well as full compliance with all Federal, State and Local laws and regulations
Take important steps to ensure all medication needs and regulatory compliance standards are met for patients
Demonstrate ethical conduct and maintain patient confidentiality at all times

What we offer

Medical, dental, and vision coverage
Paid time off
Retirement savings options
Wellness programs

Fulltime

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Staff Silicon Design Engineer (Physical Design)

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