CrawlJobs Logo

Staff Silicon Design Engineer (Physical Design)

amd.com Logo

AMD

Location Icon

Location:
Malaysia , Penang

Category Icon

Job Type Icon

Contract Type:
Employment contract

Salary Icon

Salary:

Not provided

Job Description:

We are looking for an adaptive, self-motivative Back End Physical Design engineer to join our growing team. As a key contributor, you will be part of a leading team to drive and improve AMD's abilities to deliver the highest quality, industry-leading technologies to market.

Job Responsibility:

  • Involves in Floorplan, Physical Implementation of Power-plan, Synthesis, Placement, CTS, Timing Closure, Routing, Extraction, Physical Verification (DRC & LVS), Crosstalk Analysis, EM/IR
  • Experience in handling different PNR tools - Synopsys Design Compiler, ICC2, ICC, Fusion Compiler, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk
  • Involvement in not only Physical design, but also STA & timing closure, authoring methodology scripts in Tcl, Perl and/or Python
  • Good knowledge in Physical design, STA, methodology scripts (Tcl), knowledge on Perl, Python
  • Hands on experience on 16nm, 14nm, 12nm, and sub-10nm projects

Requirements:

  • 9 years professional experience in the semiconductor industry
  • Experience in FinFET & Dual Patterning nodes such as 16/14/12 and sub-10nm nodes
  • High-frequency design experience
  • Excellent physical design and timing background
  • Synopsys Tools Experience Not a Must But Preferred
  • MNC experience is a plus
  • Familiarity with all Design areas and tools and solid understanding of design/technology interactions
  • Good understanding of computer organization/architecture
  • Strong analytical/problem solving skills and pronounced attention to details
  • Must be a self-starter, and able to independently drive tasks to completion
  • Good teamwork and communications skills are mandatory
  • Exposure/understanding on RTL is nice to have
  • Bachelors or Masters degree in computer engineering/Electrical Engineering

Nice to have:

  • Synopsys Tools Experience
  • MNC experience
  • Exposure/understanding on RTL

Additional Information:

Job Posted:
April 23, 2026

Employment Type:
Fulltime
Work Type:
Hybrid work
Job Link Share:
PREMIUM
More languages and countries
Unlock more languages and countries
Languages
English Čeština Deutsch Ελληνικά Español Français +15
Countries
United States United Kingdom India Canada Australia +
See plans
Plans from $2.99 / month

Looking for more opportunities? Search for other job offers that match your skills and interests.

Briefcase Icon

Similar Jobs for Staff Silicon Design Engineer (Physical Design)

Asic Engineer Sr Staff

Hewlett Packard Enterprise is seeking a seasoned Design-for-Test (DFT) Engineer ...
Location
Location
United States , San Jose
Salary
Salary:
148000.00 - 340500.00 USD / Year
https://www.hpe.com/ Logo
Hewlett Packard Enterprise
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • 10+ years of hands-on DFT experience in ASIC design, preferably in networking or high-speed digital domains
  • deep understanding of fault models: stuck-at, transition, path-delay
  • expertise in scan compression, ATPG, and MBIST architecture
  • experience with Siemens Tessent tools: SSN, JTAG, IJTAG, MBIST, and memory repair
  • proficiency with Synopsys tools: DFT Compiler, DFTMAX, Tetramax, Design Compiler
  • simulation experience with Synopsys VCS and Cadence NC-Verilog
  • timing analysis using PrimeTime and Cadence Tempus
  • able to define test constraints and review STA reports to ensure timing closure in test modes
  • debugging with waveform tools such as Novas and SimVision
  • familiarity with ATE pattern formats (STIL, WGL) and JTAG SVF
Job Responsibility
Job Responsibility
  • define and implement DFT architecture for high-performance networking ASICs at 3nm and beyond
  • collaborate with RTL and physical design teams to integrate scan, compression, boundary scan, and MBIST features
  • develop and validate ATPG patterns for stuck-at, transition, and path-delay fault models
  • analyze and resolve DFT-related issues including ATPG DRC violations, simulation mismatches, and timing violations
  • apply test constraints and perform STA analysis to ensure timing closure in test modes
  • support silicon bring-up and ATE pattern validation using industry-standard formats (STIL, WGL, SVF)
  • conduct silicon failure analysis and contribute to system-level debug and yield improvement
  • automate DFT flows and analysis using scripting languages such as Perl and Tcl.
What we offer
What we offer
  • health & wellbeing
  • personal & professional development
  • unconditional inclusion
  • competitive compensation, benefits, and career growth opportunities.
  • Fulltime
Read More
Arrow Right
New

Senior Quantum Design Verification Engineer

At Microsoft, our mission is to empower every person and every organization on t...
Location
Location
United States , Redmond
Salary
Salary:
119800.00 - 234700.00 USD / Year
https://www.microsoft.com/ Logo
Microsoft Corporation
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • Doctorate in Physics, Engineering, or related field AND 1+ year(s) experience in industry or in a research and development environment, could include completion of a post doctoral research position
  • OR Master's Degree in Physics, Engineering, or related field AND 4+ years experience in industry or in a research and development environment
  • OR Bachelor's Degree in Physics, Engineering, or related field AND 6+ years experience in industry or in a research and development environment
  • OR equivalent experience
  • Ability to meet Microsoft, customer and/or government security screening requirements
  • Microsoft Cloud Background Check
  • proof of citizenship or permanent residency
Job Responsibility
Job Responsibility
  • Define pre-silicon Simulation, post-silicon Validation/Characterization plans for SoC/ intellectual property (IP)
  • coordinate and drive individuals, contingent staff and external vendors towards creating a high-quality design
  • Own and create verification environments and tests for IP level and SoC level designs
  • validate designs in simulation with both pre and post layout RTL/netlists
  • Setup Databases, flows for SoC/IP repositories
  • Setup Bug-Tracking systems
  • Drive Milestone reviews, reports/status
  • Create testplans for pre-silicon simulation verification including for both digital and analog components
  • performing Analog Mixed Signal Simulation models
  • Collaborate with Design for Test (DFT) team to test DFT features
  • Fulltime
Read More
Arrow Right

Senior Staff Physical Design Engineer

We are looking for an adaptive, self-motivative physical design engineer to join...
Location
Location
Malaysia , Penang
Salary
Salary:
Not provided
amd.com Logo
AMD
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • Strong experience and specialization in deep‑submicron ASIC physical design, including all phases from RTL-to-GDSII and signoff
  • Proven record of Physical Design signoff flow
  • Hands-on experience with industry-standard EDA tools (e.g., Cadence Innovus, Tempus, PrimeTime, Fusion Compiler, Calibre)
  • Excellent scripting skills in TCL, Shell, Python, or Perl to enhance PD flows and automation
  • Proven ability to work with cross-functional teams across multiple sites/time zones
  • Strong analytical, problem-solving, and communication skills
  • Familiarity with CPU and or GPU architecture
  • Proficiency in data analysis and interpretation
Job Responsibility
Job Responsibility
  • Static Timing Analysis (STA) across MMMC scenarios: Driving timing closure at block and full‑chip levels, resolving violations through ECOs, constraint refinements, and reviewing SoC and block‑level signoff readiness. Lead timing signoff (setup, hold, OCV, AOCV/POCV, SI, CDC interfaces) across all modes and corners
  • Logic Equivalence Check (LEC) for all blocks and full‑chip: Executing equivalence verification between RTL, synthesis, and P&R databases
  • Low‑power structural checks (UPF/CLP): Ensuring correctness of power‑intent implementation, power‑domain crossings, isolation/retention, and coverage of low‑power signoff flows
  • Physical Integrity Signoff: Overseeing DRC/LVS structural verifications, and ensuring designs adhere to foundry signoff rules. Perform and review IR drop, EM, and power integrity signoff
  • Clocking and top‑level mesh implementation and signoff
  • Own and drive block-level and/or full-chip physical implementation and signoff to tape-out
  • Analyze complex cross-block and top-level signoff issues and define closure strategy
  • Define and enforce signoff criteria, methodologies, and best practices
  • Partner with PD implementation teams to guide ECO strategy for timing, power, and physical fixes
  • Identify risk areas early and proactively drive mitigation plans
Read More
Arrow Right
New

Principal Quantum Design Verification Engineer

At Microsoft Quantum, we aim to empower science and scientists to solve the worl...
Location
Location
United States , Redmond
Salary
Salary:
139900.00 - 274800.00 USD / Year
https://www.microsoft.com/ Logo
Microsoft Corporation
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • Doctorate in Physics, Engineering, or related field AND 3+ years experience in industry or in a research and development environment
  • OR Master's Degree in Physics, Engineering, or related field AND 6+ years experience in industry or in a research and development environment
  • OR Bachelor's Degree in Physics, Engineering, or related field AND 8+ years experience in industry or in a research and development environment
  • OR equivalent experience
  • Ability to meet Microsoft, customer and/or government security screening requirements
  • Microsoft Cloud Background Check
  • Citizenship & Citizenship Verification
  • Ability to leverage AI tools to drive innovation and efficiency
  • Ability to work in an 'AI-first' environment using modern AI tools to accelerate discovery through hardware development
Job Responsibility
Job Responsibility
  • Own verification environments and tests for IP and SoC designs, and validate designs in simulation with both pre- and post-layout Register-Transfer Level (RTL) and netlists
  • Coordinate the execution of contingent staff and external vendors to ensure verification deliverables meet specification and schedule
  • Set up and manage databases and flows for SoC and IP repositories
  • set up bug-tracking systems and log, track, manage, and close bugs and issues
  • drive milestone reviews and status reports
  • Create test plans for pre-silicon simulation verification across both digital and analog components, including the development of Analog Mixed-Signal (AMS) simulation models
  • Collaborate with the Design For Test (DFT) team to test DFT features
  • Align verification methodologies with wider teams and drive continuous improvement to Design Verification processes for at-scale execution
  • Collaborate effectively with architects, analog mixed-signal designers, verification engineers, and physical design, DFT, and other front-end design teams
  • Embody our culture and values
  • Fulltime
Read More
Arrow Right

Technical Manager URNANO

The candidate will independently perform complex laboratory tasks, including pla...
Location
Location
United States of America , Rochester
Salary
Salary:
77216.00 - 115824.00 USD / Year
urmc.rochester.edu Logo
University of Rochester
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • Masters degree or higher with major course work in a relevant science or engineering discipline (e.g. microelectronics/optics manufacture, applied physics, physics, chemistry, earth science, mechanical engineering, chemical engineering, biomedical engineering or related academic fields)
  • Three years of related work experience involving direct assistance to researchers
  • Three or more years of experience in managing facilities, operations, maintenance, space and equipment in a research or educational setting
  • Three or more years of experience with the operation and use of electron microscopes and associated sample preparation and characterization
  • Working knowledge of state-of-the-art scanning electron microscopes (SEM), electron spectroscopy (i.e. EDS), focused ion beam (FIB) preparation of samples, transmission electron microscopy (TEM), physical vapor deposition tools, reactive ion (plasma) processing, wafer scale silicon and associated oxide processing, soft/hard contact lithography and wet chemical processing
  • Knowledge of Intellectual property law and guidelines is a plus
  • Ability to design and properly perform all phases of set-up, operation, and repair of complex research and instructional equipment related to electron microscopy instrumentation and ancillary equipment such as specimen preparation equipment
  • Ability to apply advanced knowledge of principles, concepts and methods related to the laboratory operation, performance
  • Ability to investigate, devise and help carry out plans for continual renovation and upgrade of equipment and laboratory facilities, including potential new equipment acquisitions to advance the research capabilities of the facility
  • Ability to develop and perform complex mechanical, electrical, and/or electronic troubleshooting using technical expertise and experience
Job Responsibility
Job Responsibility
  • Provides technical operations, directs research and training, and leads efforts to advance highly specialized scientific equipment and facilities within the University of Rochester Integrated Nanosystems Center
  • Independently perform complex laboratory tasks, including planning and conducting of complete projects of limited scope and or a portion of a larger and more diverse project led by UR PIs
  • Interface as a primary trainer and mentor for complex laboratory processes for students (undergrad and graduate), faculty, staff and corporate users
  • Have both classroom and laboratory teaching duties related to microscopy and nanotechnology
  • Provides engineering services in support of engineering and physical science research activities, encompassing sample characterization, mechanical, electrical, computer, or electronic design, systems analysis, feasibility analysis, instrumentation design, etc., the solution of engineering problems, the development of engineering projects and the supervision of fabrication
  • Works independently with only occasional suggestions in modifying, varying or adapting standard laboratory procedures to meet special needs of research projects
  • Performs analyses and scientific data reductions by using standard methods and develops modifications of standard methods to meet special situations
  • Searches literature for reference to technical problems involved in research projects
  • writes standard operating procedures (SOPs)
  • prepares charts, graphs and tables
  • Fulltime
Read More
Arrow Right

Analog Design, Staff Engineer

In this role, you will work on the design, development, and refinement of Multi-...
Location
Location
Canada , Ottawa
Salary
Salary:
Not provided
synopsys.com Logo
Synopsis Engineering
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • Ph.D., M.Sc. with 3+ years, or B.Sc. with 5+ years of practical analog IC design experience
  • degree in Electrical Engineering or Computer Engineering or other relevant field of study
  • In depth familiarity with transistor level circuit design - sound CMOS design fundamentals
  • Detailed design experience with one, and familiarity with several other SERDES sub-circuits: receive equalizers, samplers, voltage/current-mode drivers, serializers, deserializers, voltage-controlled oscillator, phase mixer, delay-locked loop, phase locked loop, bandgap reference, ADC, DAC
  • Familiarity with custom digital design (i.e. high-speed logic paths)
  • Experience with analog/digital interactions for optimizing circuit performance (calibration, adaptation, timing-handoff, etc)
  • Understanding of design for reliability (i.e. EM, IR, aging, etc.) and layout effects (i.e. matching, reliability, proximity effects, etc.) as well as ESD issues (i.e. circuit techniques, layout)
  • Experience with tools for schematic entry, physical layout, and design verification
  • Understanding of SPICE simulators and simulation methods
  • Knowledgeable in Verilog-A for analog behavioral modeling and simulation-control/data-capture
Job Responsibility
Job Responsibility
  • Review SERDES standards to develop novel transceiver architectures and sub-block specifications
  • Investigate and develop circuit architectures that address architectural bottlenecks and lead to revolutionary improvements in power, area, and performance targets
  • Oversee physical layout to minimize the effect of parasitics, device stress, and process variation
  • Present and review simulation data from internal project teams
  • Document design features and test plans
  • Consult on the overall electrical characterization of the SERDES IP product. Review customer silicon data for design enhancements. Propose solutions for post-silicon design updates
What we offer
What we offer
  • Comprehensive medical and healthcare plans
  • Time Away in addition to company holidays, ETO and FTO Programs
  • Family Support including maternity and paternity leave, parenting resources, adoption and surrogacy assistance
  • ESPP - Purchase Synopsys common stock at a 15% discount
  • Retirement Plans
  • Competitive salaries
  • Fulltime
Read More
Arrow Right

Staff Engineer, VLSI Design Engineering

Sandisk understands how people and businesses consume data and we relentlessly i...
Location
Location
India , Bengaluru
Salary
Salary:
Not provided
sandisk.com Logo
Sandisk
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • B.E./B.Tech/M.E/M.S/M.Tech in electronics branches
  • Aggregate of 75% & Above in all qualifying exams
  • 4+ years of relevant Industry Experience
  • CMOS transistor level design, simulation, layout knowledge of common custom circuits like amplifiers, current mirrors, level shifters, switches, decoders
  • Knowledge of running and debugging Verilog simulations
  • Good understanding of Solid-State device physics
  • Comfortable with IC tools such as Cadence analog design environment, HSPICE/FINESIM, VCS/EXCELIUM, UNIX
  • Ability to troubleshoot and analyze complex problems
  • Excellent communication skills to effectively collaborate with Off-site counterparts across global teams
Job Responsibility
Job Responsibility
  • Designing, modifying and evaluating CMOS circuit structures for the most advanced high-performance low-power 3-dimensional NAND flash memory
  • Verify designs in simulation and interact with layout, logic and other functional groups for implementation, full chip integration and silicon validation
  • Evaluation of these circuits will be done through FINESIM and VERILOG simulations
  • Collaborate with characterization engineers to fully characterize silicon, and partner with other designers to develop solutions for silicon issues
  • Responsible for full chip silicon evaluation through probing
  • Interact with Memory Device team for transistor models, EDR/GDR requirements and tradeoffs
  • Fulltime
Read More
Arrow Right

Senior Staff Senior Silicon Design Automation Engineer

As a design engineer in our CAD and methodology team, you will be responsible fo...
Location
Location
Malaysia , Penang
Salary
Salary:
Not provided
amd.com Logo
AMD
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • TCL, Python, PERL, or other scripting languages
  • PDK, technology enablement
  • Simulation environments for Spice, PVT
  • Virtuoso based custom Layout tools and flows
  • Calibre extraction flows, Totem & Redhawk for EM/IR
  • SiliconSmart, PrimeTimePhysical aspect of VLSI designs
  • Strong written and verbal communication skills
  • Bachelors or Masters degree in computer engineering/Electrical Engineering
Job Responsibility
Job Responsibility
  • Execute in CAD infrastructure team supporting multiple IC design projects
  • Establish and maintain standardized design flows and methodologies
  • Implement and support customized CAD flows for Fabric design groups
  • Enable the team in meeting the design and development targets by working closely with external tool vendors
  • Develop tools flows methodologies on digital back-end domains, sign-off flows for timing, power, EM/IR, DRC/LVS/DFM, etc.
  • Improve engineering efficiency while improving design quality in IP release process
  • Be single point contact for bugs and issues for custom and analog physical design team
  • Build flow in TCL, Python to ensure quality and faster executions
  • Understand different methodologies used across industry to adopt best practices
  • Leverage and deploy AMD AI systems to design teams
  • Fulltime
Read More
Arrow Right