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A successful candidate will work with senior design and design verificaiton teams on the definition and execution of emulation test plans. The candidate will be highly accurate, detail-oriented, independent, and possessing good communication and problem-solving skills.
Job Responsibility
Execute emulation test plans, ensuring high-quality outcomes and adherence to timelines
Collaborate effectively with team members across North America to align on project goals, share insights, and implement best practices
Contribute in the design and implementation of emulation test benches
Contribute into continuously improving the emulation methodology
Experience implementing synthesizable models using SystemVerilog
Drive debug with designers and verifiers
Collaborate with IP design and verification teams on test planning and task execution
Work on various emulation methodologies such as: Transactors, Simulation Acceleration, Hybrid VMs
Execute verification of the latest features and protocols
Integrate, bring-up and debug standard interfaces like UART, JTAG, I2C, USB
Integrate and bring-up 3rd party accelerate verification IPs
Requirements
Experience in system and subsystem level designs
Experience with FPGA flows, synthesis and PnR
Experience in RTL design, verification, and embedded FW
Excellent programing skills in C/C++, SystemVerilog
Experience working with Verilog/SystemVerilog based designs
Experience with UVM based testbenches
Strong debugging and problem-solving skills
Debugging experience with waveform analyzers
Scripting/preprocessing
Experience working in emulation and prototyping
Understand AMBA, PCIe and CXL standards
PhD, BSc or MSc in computer science, computer engineering, or electrical engineering