Staff Physical Design Engineer Job at AMD (Penang)

Staff Silicon Design Engineer (Physical Design)

We are looking for an adaptive, self-motivative Back End Physical Design enginee...

Location

Malaysia , Penang

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

9 years professional experience in the semiconductor industry
Experience in FinFET & Dual Patterning nodes such as 16/14/12 and sub-10nm nodes
High-frequency design experience
Excellent physical design and timing background
Synopsys Tools Experience Not a Must But Preferred
MNC experience is a plus
Familiarity with all Design areas and tools and solid understanding of design/technology interactions
Good understanding of computer organization/architecture
Strong analytical/problem solving skills and pronounced attention to details
Must be a self-starter, and able to independently drive tasks to completion

Job Responsibility

Involves in Floorplan, Physical Implementation of Power-plan, Synthesis, Placement, CTS, Timing Closure, Routing, Extraction, Physical Verification (DRC & LVS), Crosstalk Analysis, EM/IR
Experience in handling different PNR tools - Synopsys Design Compiler, ICC2, ICC, Fusion Compiler, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk
Involvement in not only Physical design, but also STA & timing closure, authoring methodology scripts in Tcl, Perl and/or Python
Good knowledge in Physical design, STA, methodology scripts (Tcl), knowledge on Perl, Python
Hands on experience on 16nm, 14nm, 12nm, and sub-10nm projects

Fulltime

Staff Engineer - Physical Design

Our Hardware Engineers at Synopsys are responsible for designing and developing ...

Location

India , New Delhi

Salary:

Not provided

Synopsis Engineering

Expiration Date

Until further notice

Requirements

A minimum of 5+ years of related experience in ASIC Physical Design
Proficiency in state-of-the-art CAD tools such as DC, PT, ICC2/FC, and ICV
Experience with advanced technologies like FinFet
Strong problem-solving skills and the ability to autonomously resolve a wide range of issues
Excellent verbal and written communication skills

Job Responsibility

Implementing DDR and HBM PHYs for customer ASICs and SOCs in the DDR and HBM PHY Hardening service line
Performing synthesis, physical design, verification, design for test, and ATPG
Contributing as a senior member of a design team or as a project design engineer working with both internal and external design teams
Providing regular updates to the manager and front ending to customer on project progress
Representing the organization on business unit and/or company-wide projects
Guiding more junior peers with aspects of their job and frequently networking with senior internal and external personnel in your area of expertise

What we offer

Comprehensive medical and healthcare plans that work for you and your family
In addition to company holidays, we have ETO and FTO Programs
Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more
Purchase Synopsys common stock at a 15% discount, with a 24 month look-back
Save for your future with our retirement plans that vary by region and country
Competitive salaries

Fulltime

CPU Core Physical Design Staff Engineer

In this role, you will join the high-performance core physical design team with ...

Location

United States , Austin

Salary:

178400.00 - 267600.00 USD / Year

AMD

Expiration Date

Until further notice

Requirements

MS degree in Electrical or Computer Engineering
Mastery of logic, physical design, and CAD tools for high-performance design

Job Responsibility

Join the high-performance core physical design team with the charter to own a portion of the IP
Start with Synthesis and deliver a Placed and Routed design that meets all required criteria
Work directly with external disciplines (CAD/DFT/Architecture)
Implement working knowledge of principles of logic and transistor level circuit design, CAD tools and expertise in one of many functional areas
Innovate and improve the design
Point out lower power and higher performance tradeoffs
Preparing schedules and scope several months in advance
Prepare well thought out recommendations for technical reviews

Fulltime

Senior Staff Physical Design Engineer

We are looking for an adaptive, self-motivative physical design engineer to join...

Location

Malaysia , Penang

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

Strong experience and specialization in deep‑submicron ASIC physical design, including all phases from RTL-to-GDSII and signoff
Proven record of Physical Design signoff flow
Hands-on experience with industry-standard EDA tools (e.g., Cadence Innovus, Tempus, PrimeTime, Fusion Compiler, Calibre)
Excellent scripting skills in TCL, Shell, Python, or Perl to enhance PD flows and automation
Proven ability to work with cross-functional teams across multiple sites/time zones
Strong analytical, problem-solving, and communication skills
Familiarity with CPU and or GPU architecture
Proficiency in data analysis and interpretation

Job Responsibility

Static Timing Analysis (STA) across MMMC scenarios: Driving timing closure at block and full‑chip levels, resolving violations through ECOs, constraint refinements, and reviewing SoC and block‑level signoff readiness. Lead timing signoff (setup, hold, OCV, AOCV/POCV, SI, CDC interfaces) across all modes and corners
Logic Equivalence Check (LEC) for all blocks and full‑chip: Executing equivalence verification between RTL, synthesis, and P&R databases
Low‑power structural checks (UPF/CLP): Ensuring correctness of power‑intent implementation, power‑domain crossings, isolation/retention, and coverage of low‑power signoff flows
Physical Integrity Signoff: Overseeing DRC/LVS structural verifications, and ensuring designs adhere to foundry signoff rules. Perform and review IR drop, EM, and power integrity signoff
Clocking and top‑level mesh implementation and signoff
Own and drive block-level and/or full-chip physical implementation and signoff to tape-out
Analyze complex cross-block and top-level signoff issues and define closure strategy
Define and enforce signoff criteria, methodologies, and best practices
Partner with PD implementation teams to guide ECO strategy for timing, power, and physical fixes
Identify risk areas early and proactively drive mitigation plans

Staff Engineer, ASIC Development Engineering (Physical Design, Pnr, Floor Planning)

We are seeking a highly skilled and experienced Senior Engineer for our PNR func...

Location

India , Bangalore

Salary:

Not provided

Sandisk

Expiration Date

Until further notice

Requirements

Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field
A minimum of 5 years of experience in Place and Route Domain
Proven track record of successfully executing PNR
In-depth knowledge of PNR tools (e.g., Synopsys Fusion Compiler, Cadence Innovus) and methodologies
Strong understanding of digital design principles, physical design, and semiconductor fabrication processes
Excellent problem-solving skills and the ability to think strategically and analytically
Exceptional communication and interpersonal skills, with the ability to effectively collaborate with cross-functional teams and stakeholders
Ability to prioritize tasks and manage multiple project work simultaneously
A proactive, results-oriented mindset with a passion for innovation and continuous improvement
Experience with advanced process nodes (e.g., 7nm, 5nm) is highly desirable

Job Responsibility

Subsystem/block level ownership of Floorplanning, place and route flow for low power, high performance designs, debug of timing/power/area issues, clock tree analysis and assisting full chip timing convergence and timing closure
Collaborate with cross-function teams, including design, DFT to streamline PNR process
Drive IP integration strategies that ensure quality ASICs and avoid schedule surprises
Conduct thorough design and timing analysis, identify critical paths, and develop strategies to mitigate timing violations and improve overall design convergence
Stay abreast of industry trends and emerging technologies in PNR and related fields, and incorporate best practices into the team’s workflow
Prepare and present detailed analysis, reports and technical documentation to stakeholders
Foster a culture of innovation, collaboration, and continuous improvement within the PNR team

Fulltime

Analog Design, Staff Engineer

In this role, you will work on the design, development, and refinement of Multi-...

Location

Canada , Ottawa

Salary:

Not provided

Synopsis Engineering

Expiration Date

Until further notice

Requirements

Ph.D., M.Sc. with 3+ years, or B.Sc. with 5+ years of practical analog IC design experience
degree in Electrical Engineering or Computer Engineering or other relevant field of study
In depth familiarity with transistor level circuit design - sound CMOS design fundamentals
Detailed design experience with one, and familiarity with several other SERDES sub-circuits: receive equalizers, samplers, voltage/current-mode drivers, serializers, deserializers, voltage-controlled oscillator, phase mixer, delay-locked loop, phase locked loop, bandgap reference, ADC, DAC
Familiarity with custom digital design (i.e. high-speed logic paths)
Experience with analog/digital interactions for optimizing circuit performance (calibration, adaptation, timing-handoff, etc)
Understanding of design for reliability (i.e. EM, IR, aging, etc.) and layout effects (i.e. matching, reliability, proximity effects, etc.) as well as ESD issues (i.e. circuit techniques, layout)
Experience with tools for schematic entry, physical layout, and design verification
Understanding of SPICE simulators and simulation methods
Knowledgeable in Verilog-A for analog behavioral modeling and simulation-control/data-capture

Job Responsibility

Review SERDES standards to develop novel transceiver architectures and sub-block specifications
Investigate and develop circuit architectures that address architectural bottlenecks and lead to revolutionary improvements in power, area, and performance targets
Oversee physical layout to minimize the effect of parasitics, device stress, and process variation
Present and review simulation data from internal project teams
Document design features and test plans
Consult on the overall electrical characterization of the SERDES IP product. Review customer silicon data for design enhancements. Propose solutions for post-silicon design updates

What we offer

Comprehensive medical and healthcare plans
Time Away in addition to company holidays, ETO and FTO Programs
Family Support including maternity and paternity leave, parenting resources, adoption and surrogacy assistance
ESPP - Purchase Synopsys common stock at a 15% discount
Retirement Plans
Competitive salaries

Fulltime

Staff Actuator Design Engineer

Design, develop, and test electromechanical actuators and motor-driven mechanism...

Location

United States , Palo Alto

Salary:

220000.00 - 250000.00 USD / Year

ALSO

Expiration Date

Until further notice

Requirements

8+ years of experience designing electromechanical actuators
Deep understanding of motors, servo drives, and motion sensors
Design experience with precision motion mechanisms, including force/displacement amplification, mechanical linkages, and motion transmission systems
Ability to model mechanical behaviors of (e.g. stiffness, losses, backlash) using MATLAB/Simulink
Design experience with PCBA integration and wire harness design
Strong foundation in material properties, heat treatment, statics, and dynamics
Knowledgeable about control strategies and firmware implementation
Proficient in developing low-level drivers using Python, C, and C++
Proficient in 3D/2D CAD (Catia V5/V6 preferred) and skilled in CAE tools (Ansys, Abaqus, HyperWorks, or similar)
Strong knowledge of GD&T and tolerance stack-up analysis

Job Responsibility

Design, develop, and test electromechanical actuators and motor-driven mechanisms for light electric vehicle platforms
Create detailed drawing packages and manufacturing instructions for mechanical parts and assemblies
Perform 3D modeling of components and assemblies, including die castings, injection-molded plastics, sheet metal, and fasteners
Collaborate with electrical engineers to integrate PCBAs, wire harnesses, and electronic systems into mechanical designs
Collaborate with firmware engineers to ensure physical systems support robust control and seamless integration with embedded software
Coordinate validation efforts with Tier 1 and Tier 2 suppliers
Develop and execute design verification plans and reports (DVP&R)
Lead and maintain design failure mode and effects analyses (DFMEAs)
Prototype and iterate designs using hands-on fabrication and lab testing to validate functionality

What we offer

Robust health coverage. Excellent health, dental and vision insurance covered up to 100% by ALSO with FSA & HSA options
One Medical membership and dedicated insurance advocates
Rich fertility and family building benefits with Progyny
Flexible time off
401(k) match

Fulltime

Staff Analog Design Engineer

Our Hardware Engineers at Synopsys are responsible for designing and developing ...

Location

India , Hyderabad

Salary:

Not provided

Synopsis Engineering

Expiration Date

Until further notice

Requirements

MTech/MS with 4+ years or BTech/BS with 5+ years of practical analog IC design experience in Electrical or Computer Engineering (or related field)
Proven expertise with FinFET technologies and CMOS tape-outs
Deep understanding of Multi-Gbps high-speed designs (PAM4, NRZ) and SERDES architectures
Extensive design experience with SERDES sub-circuits (e.g., TX, RX, adaptive equalizers, PLL, DLL, BGR, regulators, oscillators, ADC/DAC)
Skilled in analog/digital co-design, calibration, adaptation, and timing handoff for optimized circuit performance
Familiarity with ESD protection, custom digital design, and design for reliability (EM, IR, aging, self-heating)
Proficient with schematic entry, physical layout, design verification tools, and SPICE simulators
Experience with scripting languages (TCL, PERL, MATLAB) for post-processing simulation results
Understanding of system-level budgeting (jitter, amplitude, noise) and signal integrity (packaging, parasitics, crosstalk)
Excellent communication and documentation skills

Job Responsibility

Reviewing SerDes standards to develop novel transceiver architectures and detailed sub-block specifications
Investigating and architecting circuit solutions that address performance bottlenecks, enabling significant improvements in power, area, and speed
Collaborating with cross-functional analog and digital design teams to streamline design and verification processes for optimal efficiency and quality
Overseeing and guiding the physical layout to minimize parasitics, device stress, and process variations, ensuring robust silicon performance
Presenting and reviewing simulation data with internal teams and external stakeholders, including industry panels and customer reviews
Documenting design features, test plans, and results, and consulting on electrical characterization and post-silicon analysis for product enhancements
Analyzing customer silicon data to identify design improvement opportunities and proposing solutions for post-silicon updates

What we offer

Comprehensive medical and healthcare plans that work for you and your family
Time Away: In addition to company holidays, we have ETO and FTO Programs
Family Support: Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more
ESPP: Purchase Synopsys common stock at a 15% discount, with a 24 month look-back
Retirement Plans: Save for your future with our retirement plans that vary by region and country
Competitive salaries

Fulltime

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Staff Physical Design Engineer

Job Description

Job Responsibility

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