Staff Engineer, VLSI Design Engineering Job at Sandisk (Bengaluru)

Staff Engineer, VLSI Design Engineering

Develop test plans, tests and verification infrastructure for a complex IP/Sub-S...

Location

India , Bengaluru

Salary:

Not provided

Sandisk

Expiration Date

Until further notice

Requirements

5 to 7 years of relevant experience
B.E/B.Tech/M.Tech in ECE/VLSI/Electrical Engineering
Proficiency in Computer Science fundamentals – object oriented design, data structures, algorithms, design, problem solving, and complexity analysis
Basic knowledge of with c, c++, SystemC, perl, python, tcl, shell is preferable
Unit/Sub-system/SOC level verification experience
Experience in leading verification closure of complex IP/SOC for at least one project
Exposure to industry standard verification tools for simulation and debug
RTL & Gate Level Simulations
Proficiency in Verilog, System Verilog, Assertions and UVM
Exposure to Verification Fundamentals

Job Responsibility

Develop test plans, tests and verification infrastructure for a complex IP/Sub-System or lead major deliverables for SoC
Create verification environment using UVM methodology
Hands on in end to end Logic Verification Process including Verification Planning, Functional Coverage planning and development, Test case development, regression, debug and Coverage closure
Create reusable bus functional models, monitors, checkers and scoreboards
Drive functional coverage driven verification closure
Work with architects, designers, and post-silicon teams
Hands-on contributions to SVA development like coding, porting and maintaining System Verilog Assertions including Formal Verification
Development of tools for Design and Verification support
Debug failures and root-cause it by interacting with other teams/groups

Fulltime

Staff Engineer, VLSI Design Engineering

We are looking for a highly motivated engineer to develop synthesizable RTL mode...

Location

India , Bangalore

Salary:

Not provided

Sandisk

Expiration Date

Until further notice

Requirements

4 to 7 years of experience in RTL design, UVM validation, and emulation support
Bachelors/Masters from a reputed College/University with Electronics and communication/Embedded Systems background
Strong Problem Solving and Debug skills
Efficient Communication
Strong expertise in Verilog/SystemVerilog RTL coding and digital design fundamentals
Hands-on experience with UVM methodology and testbench development
Familiarity with emulation platforms (e.g., Cadence Palladium, Protium, Synopsys ZeBu, Mentor Veloce)
Proficiency in simulation tools (e.g., VCS, Questa, Xcelium) and waveform debug
Scripting skills in Python, TCL, or Perl for automation and testbench control
Understanding of SoC architecture, clock/reset domains, and interface protocols (AXI, APB, PCIe, etc.)

Job Responsibility

Develop clean, synthesizable RTL models for IP blocks and subsystems using Verilog/SystemVerilog
Collaborate with design teams to ensure RTL is emulation-friendly and meets performance and debug requirements
Create and maintain UVM-based testbenches to validate RTL functionality and coverage
Debug RTL and testbench issues using simulation and emulation tools
Package and deliver validated RTL models to the emulation team, including synthesis scripts, configuration files, and documentation
Support emulation bring-up and assist in resolving integration issues

Fulltime

Staff Engineer, VLSI Design Engineering

Sandisk understands how people and businesses consume data and we relentlessly i...

Location

India , Bengaluru

Salary:

Not provided

Sandisk

Expiration Date

Until further notice

Requirements

B.E./B.Tech/M.E/M.S/M.Tech in electronics branches
Aggregate of 75% & Above in all qualifying exams
4+ years of relevant Industry Experience
CMOS transistor level design, simulation, layout knowledge of common custom circuits like amplifiers, current mirrors, level shifters, switches, decoders
Knowledge of running and debugging Verilog simulations
Good understanding of Solid-State device physics
Comfortable with IC tools such as Cadence analog design environment, HSPICE/FINESIM, VCS/EXCELIUM, UNIX
Ability to troubleshoot and analyze complex problems
Excellent communication skills to effectively collaborate with Off-site counterparts across global teams

Job Responsibility

Designing, modifying and evaluating CMOS circuit structures for the most advanced high-performance low-power 3-dimensional NAND flash memory
Verify designs in simulation and interact with layout, logic and other functional groups for implementation, full chip integration and silicon validation
Evaluation of these circuits will be done through FINESIM and VERILOG simulations
Collaborate with characterization engineers to fully characterize silicon, and partner with other designers to develop solutions for silicon issues
Responsible for full chip silicon evaluation through probing
Interact with Memory Device team for transistor models, EDR/GDR requirements and tradeoffs

Fulltime

Staff Engineer, VLSI Design Engineering

We are looking for a highly motivated engineer to develop synthesizable RTL mode...

Location

India , Bengaluru

Salary:

Not provided

Sandisk

Expiration Date

Until further notice

Requirements

4 to 7 years of experience in RTL design, UVM validation, and emulation support
Bachelors/Masters from a reputed College/University with Electronics and communication/Embedded Systems background
Strong Problem Solving and Debug skills
Efficient Communication
Strong expertise in Verilog/SystemVerilog RTL coding and digital design fundamentals
Hands-on experience with UVM methodology and testbench development
Familiarity with emulation platforms (e.g., Cadence Palladium, Protium, Synopsys ZeBu, Mentor Veloce)
Proficiency in simulation tools (e.g., VCS, Questa, Xcelium) and waveform debug
Scripting skills in Python, TCL, or Perl for automation and testbench control
Understanding of SoC architecture, clock/reset domains, and interface protocols (AXI, APB, PCIe, etc.)

Job Responsibility

Develop clean, synthesizable RTL models for IP blocks and subsystems using Verilog/SystemVerilog
Collaborate with design teams to ensure RTL is emulation-friendly and meets performance and debug requirements
Create and maintain UVM-based testbenches to validate RTL functionality and coverage
Debug RTL and testbench issues using simulation and emulation tools
Package and deliver validated RTL models to the emulation team, including synthesis scripts, configuration files, and documentation
Support emulation bring-up and assist in resolving integration issues

Fulltime

Staff Engineer, VLSI Design Engineering (Analog Design)

Successful candidates will work with the Non-volatile Memory Design team to arch...

Location

India , Bengaluru

Salary:

Not provided

Sandisk

Expiration Date

Until further notice

Requirements

BTech/MTech from Premier institute
4+ years design experience in Analog Circuits like Amplifiers, Bandgap, LDOs, Oscillators, switching circuit etc.
Understanding of layout and its impact on circuits
Well versed with industry tools to do analog design
Exposure to full chip simulations
Excellent documentation skills
Written and verbal communication skills
Good Team player, flexible and adapting to learn outside analog design e.g system integration, silicon validation

Job Responsibility

Design, simulate, and verify critical circuits like Voltage regulators, LDO, Current and Voltage reference, High Voltage charge pumps, temperature sensors, oscillators etc using industry standard EDA tools
Work with layout engineers and closely interact during the design phase by reviewing layout and providing input as needed and perform post layout simulations (Back-annotation) of Analog blocks
Participate in Full chip verification to ensure analog block functionality at chip level
Build understanding on the analog function/circuit usage in system and its impact on chip power/area/performance
Detailed Documentation of Module specifications, signal list, layout guidelines and Checklist
Propose innovative circuit solutions and design methodologies. Document and present new architectures, new and enhanced circuit designs, and simulation results during design reviews
Verify and characterize silicon using lab equipment’s and testers. Corelate the simulation data with silicon data and document the learning
Mentor junior engineers to learn and deliver the assignment
Ensure timelines and quality of assigned assignments

Fulltime

Staff Engineer, VLSI Design Engineering (Analog Design)

Successful candidates will work with the Non-volatile Memory Design team to arch...

Location

India , Bengaluru

Salary:

Not provided

Sandisk

Expiration Date

Until further notice

Requirements

BTech/MTech from Premier institute
4+ years design experience in Analog Circuits like Amplifiers, Bandgap, LDOs, Oscillators, switching circuit etc.
Understanding of layout and its impact on circuits
Well versed with industry tools to do analog design
Exposure to full chip simulations
Excellent documentation skills
Written and verbal communication skills
Good Team player, flexible and adapting to learn outside analog design e.g. system integration, silicon validation

Job Responsibility

Design, simulate, and verify critical circuits like Voltage regulators, LDO, Current and Voltage reference, High Voltage charge pumps, temperature sensors, oscillators etc. using industry standard EDA tools
Work with layout engineers and closely interact during the design phase by reviewing layout and providing input as needed and perform post layout simulations (Back-annotation) of Analog blocks
Participate in Full chip verification to ensure analog block functionality at chip level
Build understanding on the analog function/circuit usage in system and its impact on chip power/area/performance
Detailed Documentation of Module specifications, signal list, layout guidelines and Checklist
Propose innovative circuit solutions and design methodologies. Document and present new architectures, new and enhanced circuit designs, and simulation results during design reviews
Verify and characterize silicon using lab equipment’s and testers. Corelate the simulation data with silicon data and document the learning
Mentor junior engineers to learn and deliver the assignment
Ensure timelines and quality of assigned assignments

Fulltime

Staff Physical Design Engineer

We are looking for an adaptive, self-motivative physical design engineer to join...

Location

Malaysia , Penang

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

8+ years of professional experience in physical design, preferably with high-performance designs
Must have closed high-performance IPs- CPU/GPU/DPU/memory controller, etc.
Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality
familiarity with tools for schematics, layout, and circuit/logic simulation
Versatility with scripts to automate design flow - Perl/Tcl/Python
Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams
Experience in advanced sub 7nm nodes
Excellent physical design and timing background
A good understanding of computer architecture is preferred
Strong analytical/problem-solving skills and pronounced attention to detail

Job Responsibility

Own critical GPU units and drive to convergence from RTL-to-GDSII - synthesis, floor-planning, place and route, timing closure, and signoff
Understand the micro-architecture to perform feasibility studies on performance, power, and area (PPA) tradeoffs for design closure
Develop and improve physical design methodologies and customize recipes across various implementation steps to optimize PPA
Implement floor plan, synthesis, placement, CTS, Timing Closure, Routing, Extraction, Physical Verification (DRC & LVS), EM/IR and signoff
Handling different PNR tools - Synopsys fusion compiler, Cadence, PrimeTime, StarRC, Calibre, Apache Redhawk

Staff Engineer, ASIC Development Engineering

Sandisk’s ASIC team builds state-of-the-art memory controllers that power world-...

Location

India , Bengaluru

Salary:

Not provided

Sandisk

Expiration Date

Until further notice

Requirements

3-5 years of experience in mixed-signal / analog design, custom layout, CAD, or methodology roles
Strong understanding of transistor-level circuit design, including device behavior, biasing, matching, noise, and variability
Hands-on experience with custom layout design and a deep appreciation of layout quality and its impact on circuit performance
Expertise in physical verification and signoff, including: DRC, LVS, PERC
EM/IR and reliability signoff tools
Proven experience architecting custom design and verification methodologies for mixed-signal IPs
Strong understanding of interactions between circuit design, layout parasitics, and signoff requirements
Proficiency in scripting and automation using SVRF, SKILL, TCL, Python, and/or Perl
M.Tech / MS in VLSI Design, Microelectronics, or a related field (or equivalent industry experience)

Job Responsibility

Mixed-signal IP CAD and methodology development, covering schematic, layout, verification, and signoff flows
Architect and maintain end-to-end custom design methodologies, from transistor-level design through signoff-ready layouts
Drive layout quality standards, including matching, symmetry, parasitic control, reliability, and manufacturability
Define and enforce physical verification methodologies, including: DRC
LVS
PERC
Reliability and signoff checks
Own and evolve signoff methodologies for mixed-signal IPs, including EM/IR analysis and reliability verification
Work closely with custom circuit designers and layout teams to identify recurring issues and introduce automation, checks, and best practices
Collaborate with foundry counterparts to understand process-specific constraints, reliability requirements, and rule interpretations

Fulltime

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Staff Engineer, VLSI Design Engineering

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