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Staff Engineer, VLSI Design Engineering

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Sandisk

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Location:
India , Bengaluru

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Category:
IT - Software Development

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Contract Type:
Not provided

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Salary:

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Job Description:

Develop test plans, tests and verification infrastructure for a complex IP/Sub-System or lead major deliverables for SoC. Create verification environment using UVM methodology. Hands on in end to end Logic Verification Process including Verification Planning, Functional Coverage planning and development, Test case development, regression, debug and Coverage closure. Create reusable bus functional models, monitors, checkers and scoreboards. Drive functional coverage driven verification closure. Work with architects, designers, and post-silicon teams. Hands-on contributions to SVA development like coding, porting and maintaining System Verilog Assertions including Formal Verification. Development of tools for Design and Verification support. Debug failures and root-cause it by interacting with other teams/groups Etc.

Job Responsibility:

  • Develop test plans, tests and verification infrastructure for a complex IP/Sub-System or lead major deliverables for SoC
  • Create verification environment using UVM methodology
  • Hands on in end to end Logic Verification Process including Verification Planning, Functional Coverage planning and development, Test case development, regression, debug and Coverage closure
  • Create reusable bus functional models, monitors, checkers and scoreboards
  • Drive functional coverage driven verification closure
  • Work with architects, designers, and post-silicon teams
  • Hands-on contributions to SVA development like coding, porting and maintaining System Verilog Assertions including Formal Verification
  • Development of tools for Design and Verification support
  • Debug failures and root-cause it by interacting with other teams/groups

Requirements:

  • 5 to 7 years of relevant experience
  • B.E/B.Tech/M.Tech in ECE/VLSI/Electrical Engineering
  • Proficiency in Computer Science fundamentals – object oriented design, data structures, algorithms, design, problem solving, and complexity analysis
  • Basic knowledge of with c, c++, SystemC, perl, python, tcl, shell is preferable
  • Unit/Sub-system/SOC level verification experience
  • Experience in leading verification closure of complex IP/SOC for at least one project
  • Exposure to industry standard verification tools for simulation and debug
  • RTL & Gate Level Simulations
  • Proficiency in Verilog, System Verilog, Assertions and UVM
  • Exposure to Verification Fundamentals
  • Verification Automation using scripts like Python, Perl,shell,tcl/tk
  • Good debugging and problem solving skills
  • Good communication skills and ability, desire to work as a team player
  • Exposure to Analog verification will additional plus point
  • CMOS VLSI, Digital Circuits
  • Knowledge on Memory (preferred) (SRAM/DRAM/ROM/Flash) Circuits/Logic
  • Preferred exposure - NCSIM, Xcellium, IMC, IEV, Verdi, Jaspergold, VS Formal
  • Preferred exposure - Cadence Schematic and layout environment

Nice to have:

  • Exposure to Analog verification
  • Knowledge on Memory (SRAM/DRAM/ROM/Flash) Circuits/Logic
  • Preferred exposure to NCSIM, Xcellium, IMC, IEV, Verdi, Jaspergold, VS Formal
  • Preferred exposure to Cadence Schematic and layout environment

Additional Information:

Job Posted:
January 20, 2026

Employment Type:
Fulltime
Work Type:
On-site work
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