Staff Engineer, VLSI Design Engineering

• Develop clean, synthesizable RTL models for IP blocks and subsystems using Verilog/SystemVerilog
• Collaborate with design teams to ensure RTL is emulation-friendly and meets performance and debug requirements
• Create and maintain UVM-based testbenches to validate RTL functionality and coverage
• Debug RTL and testbench issues using simulation and emulation tools
• Package and deliver validated RTL models to the emulation team, including synthesis scripts, configuration files, and documentation
• Support emulation bring-up and assist in resolving integration issues

• 4 to 7 years of experience in RTL design, UVM validation, and emulation support
• Bachelors/Masters from a reputed College/University with Electronics and communication/Embedded Systems background
• Strong Problem Solving and Debug skills
• Efficient Communication
• Strong expertise in Verilog/SystemVerilog RTL coding and digital design fundamentals
• Hands-on experience with UVM methodology and testbench development
• Familiarity with emulation platforms (e.g., Cadence Palladium, Protium, Synopsys ZeBu, Mentor Veloce)
• Proficiency in simulation tools (e.g., VCS, Questa, Xcelium) and waveform debug
• Scripting skills in Python, TCL, or Perl for automation and testbench control
• Understanding of SoC architecture, clock/reset domains, and interface protocols (AXI, APB, PCIe, etc.)
• Must have strong hold on Digital Design Concepts Circuits/Logic
• Customer Interactions and support required for delivered model
• Debug failures and root-cause it by interacting with other teams/groups

Knowledge on Memory would be preferable (SRAM/DRAM/ROM/Flash)