Staff Engineer, ASIC Development Engineering Job at Sandisk (Bengaluru)

Staff Engineer, ASIC Development Engineering

Sandisk’s ASIC team builds state-of-the-art memory controllers that power world-...

Location

India , Bengaluru

Salary:

Not provided

Sandisk

Expiration Date

Until further notice

Requirements

3-5 years of experience in mixed-signal / analog design, custom layout, CAD, or methodology roles
Strong understanding of transistor-level circuit design, including device behavior, biasing, matching, noise, and variability
Hands-on experience with custom layout design and a deep appreciation of layout quality and its impact on circuit performance
Expertise in physical verification and signoff, including: DRC, LVS, PERC
EM/IR and reliability signoff tools
Proven experience architecting custom design and verification methodologies for mixed-signal IPs
Strong understanding of interactions between circuit design, layout parasitics, and signoff requirements
Proficiency in scripting and automation using SVRF, SKILL, TCL, Python, and/or Perl
M.Tech / MS in VLSI Design, Microelectronics, or a related field (or equivalent industry experience)

Job Responsibility

Mixed-signal IP CAD and methodology development, covering schematic, layout, verification, and signoff flows
Architect and maintain end-to-end custom design methodologies, from transistor-level design through signoff-ready layouts
Drive layout quality standards, including matching, symmetry, parasitic control, reliability, and manufacturability
Define and enforce physical verification methodologies, including: DRC
LVS
PERC
Reliability and signoff checks
Own and evolve signoff methodologies for mixed-signal IPs, including EM/IR analysis and reliability verification
Work closely with custom circuit designers and layout teams to identify recurring issues and introduce automation, checks, and best practices
Collaborate with foundry counterparts to understand process-specific constraints, reliability requirements, and rule interpretations

Fulltime

Staff Engineer, ASIC development Engineering

As a SoC Validation/Verification Engineer, you will play a key role in ensuring ...

Location

India , Bangalore

Salary:

Not provided

Sandisk

Expiration Date

Until further notice

Requirements

BE or MS degree in Electrical Engineering or Computer Engineering
5-8+ years of experience in SoC pre-/post-silicon verification and validation, and bring-up
Deep understanding of C, embedded programming, and hardware/software co-validation methodologies
Strong knowledge of SoC verification environments, SystemVerilog (SV), and UVM concepts
Proven history of developing and executing verification and validation strategies for complex SoCs
Experience in verification and validation of industry-standard protocols such as DDR, PCIe, LPDDR, USB, Ethernet, I²C, I3C, SPI, AXI, AHB, and APB
Must understand and contribute to complex SoC-level testbenches, including UVM, C, and SystemVerilog components
Strong experience in bring-up, including board initialization, power-on sequences, processor boot, and system-level debug for both pre- and post-silicon phases
Hands-on experience in post-silicon ASIC bring-up, validation, and debug
Should have a very good understanding of C, Python, or Perl scripting languages for test automation, data analysis, and tool development

Job Responsibility

Understanding complex ASIC specifications to create comprehensive Verification/Validation plans for both pre- and post-silicon validation
Independently developing and executing tests for verification and validation
Collaborating with cross-functional teams to drive closure of verification and validation activities
Signing off on verification and validation deliverables
Debugging and root cause analysis of issues found during validation
Developing and maintaining automated test environments and regression suites
Contributing to the continuous improvement of verification methodologies and best practices
End-to-end ownership of one or more subsystems or SoC verification and validation flows, including planning, execution, and closure
Run complex SoC verification and validation scenarios on Palladium/Emulation platforms to accelerate debug and improve pre-silicon coverage
Execute verification and validation cases in simulation environments and perform initial debug and root cause analysis

Fulltime

Staff Engineer, ASIC Development Engineering

Are you ready to push the boundaries of what's possible in technology? Join the ...

Location

India , Bengaluru

Salary:

Not provided

Sandisk

Expiration Date

Until further notice

Requirements

Bachelor’s or master’s degree in electrical engineering, Computer Engineering, or a related field with 5-8 years of experience
Proven experience in ASIC RTL design, with a strong grasp of Verilog/System Verilog
Strong understanding of SoC architecture, AMBA protocols (AXI/AHB/APB), interconnects and peripherals for debug
Prior knowledge of Power Intent format (UPF) and Timing Constraints (SDC) is a must
Proficiency in scripting languages (e.g., Python, TCL) for automation
Hands-on with EDA tools (simulation, lint, CDC, synthesis, formal verification)
Strong problem-solving skills and the ability to thrive in a dynamic environment
Excellent communication and teamwork abilities

Job Responsibility

Innovate and develop RTL code for complex ASICs
Contribute in SoC subsystems related to CPU complex, DDR, Host, Flash, Debug, Clocks, resets, Power domains etc. for top of the line flash controllers
Ensure robust design methodologies including Lint, CDC, RDC, CLP and FC-Elab
Utilize advanced AI-driven tools, including GitHub Copilot, to streamline the design process
Collaborate with DFT, PD, Hardware and Firmware teams for delivering the most optimal solution
Work along side with the SoC Managers and SoC Leads to deliver best-in-class solution
Stay abreast of the latest industry trends and emerging technologies in AI and ASIC design

Fulltime

Staff Engineer, ASIC Development Engineering

Sandisk understands how people and businesses consume data and we relentlessly i...

Location

India , Bengaluru

Salary:

Not provided

Sandisk

Expiration Date

Until further notice

Requirements

Bachelor's or Master's degree in Electrical/Electronic Engineering or a related field
4-8 years of experience in digital design, with a strong focus on RTL design and integration for complex SoCs
Expert-level proficiency in Verilog/SystemVerilog
Deep understanding of AMBA protocols (AXI/AHB/APB), interconnects, and peripherals
Experience in ASIC verification, Expertise in System Verilog and UVM, Verilog
Experience in IP level verification, testbench architecture development, Testbench component developments
Expertise in coverage closer, code coverage, functional coverage
Experience in Gate level simulations
Knowledge on serial protocols UFS, PCIe, USB, MIPI or any other serial protocol
Knowledge on memory protocols - SD, eMMC, Flash etc

Job Responsibility

Define verification plan, create testbenches, testcases, gate level simulations etc independently

Fulltime

Staff Engineer, ASIC Development Engineering

Are you ready to push the boundaries of what's possible in technology? Join the ...

Location

India , Bangalore

Salary:

Not provided

Sandisk

Expiration Date

Until further notice

Requirements

Bachelor’s or master’s degree in electrical engineering, Computer Engineering, or a related field with 5-8 years of experience
Proven experience in ASIC RTL design, with a strong grasp of Verilog/System Verilog
Strong understanding of SoC architecture, AMBA protocols (AXI/AHB/APB), interconnects and peripherals for debug
Prior knowledge of Power Intent format (UPF) and Timing Constraints (SDC) is a must
Proficiency in scripting languages (e.g., Python, TCL) for automation
Hands-on with EDA tools (simulation, lint, CDC, synthesis, formal verification)
Strong problem-solving skills and the ability to thrive in a dynamic environment
Excellent communication and teamwork abilities

Job Responsibility

Innovate and develop RTL code for complex ASICs
Contribute in SoC subsystems related to CPU complex, DDR, Host, Flash, Debug, Clocks, resets, Power domains etc. for top of the line flash controllers
Ensure robust design methodologies including Lint, CDC, RDC, CLP and FC-Elab
Utilize advanced AI-driven tools, including GitHub Copilot, to streamline the design process
Collaborate with DFT, PD, Hardware and Firmware teams for delivering the most optimal solution
Work along side with the SoC Managers and SoC Leads to deliver best-in-class solution
Stay abreast of the latest industry trends and emerging technologies in AI and ASIC design

Fulltime

Staff Engineer, ASIC Development Engineering

Are you ready to push the boundaries of what's possible in technology? Join the ...

Location

India , Bengaluru

Salary:

Not provided

Sandisk

Expiration Date

Until further notice

Requirements

Bachelor’s or master’s degree in electrical engineering, Computer Engineering, or a related field with 5-8 years of experience
Proven experience in ASIC RTL design, with a strong grasp of Verilog/System Verilog
Strong understanding of SoC architecture, AMBA protocols (AXI/AHB/APB), interconnects and peripherals for debug
Prior knowledge of Power Intent format (UPF) and Timing Constraints (SDC) is a must
Proficiency in scripting languages (e.g., Python, TCL) for automation
Hands-on with EDA tools (simulation, lint, CDC, synthesis, formal verification)
Strong problem-solving skills and the ability to thrive in a dynamic environment
Excellent communication and teamwork abilities

Job Responsibility

Innovate and develop RTL code for complex ASICs
Contribute in SoC subsystems related to CPU complex, DDR, Host, Flash, Debug, Clocks, resets, Power domains etc. for top of the line flash controllers
Ensure robust design methodologies including Lint, CDC, RDC, CLP and FC-Elab
Utilize advanced AI-driven tools, including GitHub Copilot, to streamline the design process
Collaborate with DFT, PD, Hardware and Firmware teams for delivering the most optimal solution
Work along side with the SoC Managers and SoC Leads to deliver best-in-class solution
Stay abreast of the latest industry trends and emerging technologies in AI and ASIC design

Fulltime

Staff Engineer, ASIC Development Engineering

We are seeking a highly skilled High-speed SERDES IO PHY Layout designer with 5 ...

Location

India , Bengaluru

Salary:

Not provided

Sandisk

Expiration Date

Until further notice

Requirements

Bachelor’s or Master’s degree in Electrical Engineering, Electronics, or a related field
5-10 years of experience in IO/Analog mixed-signal IC layout design and block level PnR
Proficiency in layout tools such as Cadence, Synopsys, or Mentor Graphics
Hands-on experience with custom layout design for various analog and IO circuits is required, including expertise in Bandgap references, LDOs, Clocking circuits, GPIOs, DDR IOs, and ESD circuits
Familiarity with custom digital layout (i.e. high speed logic paths)
Knowledge of signal integrity issues (i.e. clock/data routes, differential routing, shielding)
Strong understanding of analog/IO design principles, including parasitic effects
Aware of layout techniques to mitigate ESD, latch-up issues
Holds advanced knowledge of CMOS and FinFET technologies and their impact on design and performance issues in deep sub-micron process nodes, specifically 7nm and below
Experience with layout concepts that incorporate reliability considerations, including techniques for managing electromigration (EM), IR drop, and self-heating

Job Responsibility

Develop and optimize Serdes PHY, analog and mixed-signal IC layouts, ensuring high performance and manufacturability
Collaborate with design engineers to understand design requirements and translate them into precise layouts
Strong experience in debugging DRC, ERC, LVS, EMIR and PERC issues independently
Work experience of block PnR to closely interact with physical design team ensuring area/timing/backend compatibility of custom blocks into the overall chip design
Identify and resolve layout-related issues, providing creative solutions to meet design specifications
Conduct layout reviews and provide technical feedback to improve layout practices and methodologies
Stay up-to-date with industry trends, tools, and technologies to continuously enhance layout processes

Fulltime

Staff Engineer, ASIC Development Engineering (STA, PNR and Timing)

We are seeking a highly skilled and experienced Staff Engineer for our Static Ti...

Location

India , Bengaluru

Salary:

Not provided

Sandisk

Expiration Date

Until further notice

Requirements

Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field
A minimum of 5 years of experience in Static Timing Analysis
Proven track record of successfully executing STA
In-depth knowledge of STA tools (e.g., Synopsys PrimeTime, Cadence Tempus , Constraints Manager) and methodologies
Strong understanding of digital design principles, physical design, and semiconductor fabrication processes
Excellent problem-solving skills and the ability to think strategically and analytically
Exceptional communication and interpersonal skills, with the ability to effectively collaborate with cross-functional teams and stakeholders
Ability to prioritize tasks and manage multiple project work simultaneously
A proactive, results-oriented mindset with a passion for innovation and continuous improvement
Experience with advanced process nodes (e.g., 7nm, 5nm) is highly desirable

Job Responsibility

Own Subsystem level STA , providing direction and guidance to PnR team for Timing closure & Synthesis report analysis
Work with IP & Design team for Timing constraints Development & Review activities
Develop and implement advanced STA methodologies and strategies to meet the timing closure requirements of complex IC designs
Collaborate with cross-functional teams, including design, verification, physical design, and DFT, to ensure seamless integration and optimal timing performance
Drive the development and maintenance of STA scripts and tools to automate and streamline timing analysis processes
Conduct thorough timing analysis, identify critical paths, and develop strategies to mitigate timing violations and improve overall design performance
Stay abreast of industry trends and emerging technologies in STA and related fields, and incorporate best practices into the team’s workflow
Prepare and present detailed timing reports and technical documentation to stakeholders
Foster a culture of innovation, collaboration, and continuous improvement within the STA team

Fulltime

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Staff Engineer, ASIC Development Engineering

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Staff Engineer, ASIC Development Engineering

Staff Engineer, ASIC Development Engineering

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Staff Engineer, ASIC Development Engineering

Staff Engineer, ASIC Development Engineering

Staff Engineer, ASIC Development Engineering

Staff Engineer, ASIC Development Engineering

Staff Engineer, ASIC Development Engineering

Staff Engineer, ASIC Development Engineering (STA, PNR and Timing)

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