Staff Engineer, ASIC Development Engineering (STA) Job at Sandisk (Bengaluru)

Staff Engineer, ASIC Development Engineering (STA)

We are seeking a highly skilled and experienced Staff Engineer for our Static Ti...

Location

India , Bengaluru

Salary:

Not provided

Sandisk

Expiration Date

Until further notice

Requirements

Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field
A minimum of 5 years of experience in Static Timing Analysis
Proven track record of successfully executing STA
In-depth knowledge of STA tools (e.g., Synopsys PrimeTime, Cadence Tempus , Constraints Manager) and methodologies
Strong understanding of digital design principles, physical design, and semiconductor fabrication processes
Excellent problem-solving skills and the ability to think strategically and analytically
Exceptional communication and interpersonal skills, with the ability to effectively collaborate with cross-functional teams and stakeholders
Ability to prioritize tasks and manage multiple project work simultaneously
A proactive, results-oriented mindset with a passion for innovation and continuous improvement
Experience with advanced process nodes (e.g., 7nm, 5nm) is highly desirable

Job Responsibility

Own Subsystem level STA , providing direction and guidance to PnR team for Timing closure & Synthesis report analysis
Work with IP & Design team for Timing constraints Development & Review activities
Develop and implement advanced STA methodologies and strategies to meet the timing closure requirements of complex IC designs
Collaborate with cross-functional teams, including design, verification, physical design, and DFT, to ensure seamless integration and optimal timing performance
Drive the development and maintenance of STA scripts and tools to automate and streamline timing analysis processes
Conduct thorough timing analysis, identify critical paths, and develop strategies to mitigate timing violations and improve overall design performance
Stay abreast of industry trends and emerging technologies in STA and related fields, and incorporate best practices into the team’s workflow
Prepare and present detailed timing reports and technical documentation to stakeholders
Foster a culture of innovation, collaboration, and continuous improvement within the STA team

Fulltime

Staff Engineer, ASIC Development Engineering (STA, PNR and Timing)

We are seeking a highly skilled and experienced Staff Engineer for our Static Ti...

Location

India , Bengaluru

Salary:

Not provided

Sandisk

Expiration Date

Until further notice

Requirements

Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field
A minimum of 5 years of experience in Static Timing Analysis
Proven track record of successfully executing STA
In-depth knowledge of STA tools (e.g., Synopsys PrimeTime, Cadence Tempus , Constraints Manager) and methodologies
Strong understanding of digital design principles, physical design, and semiconductor fabrication processes
Excellent problem-solving skills and the ability to think strategically and analytically
Exceptional communication and interpersonal skills, with the ability to effectively collaborate with cross-functional teams and stakeholders
Ability to prioritize tasks and manage multiple project work simultaneously
A proactive, results-oriented mindset with a passion for innovation and continuous improvement
Experience with advanced process nodes (e.g., 7nm, 5nm) is highly desirable

Job Responsibility

Own Subsystem level STA , providing direction and guidance to PnR team for Timing closure & Synthesis report analysis
Work with IP & Design team for Timing constraints Development & Review activities
Develop and implement advanced STA methodologies and strategies to meet the timing closure requirements of complex IC designs
Collaborate with cross-functional teams, including design, verification, physical design, and DFT, to ensure seamless integration and optimal timing performance
Drive the development and maintenance of STA scripts and tools to automate and streamline timing analysis processes
Conduct thorough timing analysis, identify critical paths, and develop strategies to mitigate timing violations and improve overall design performance
Stay abreast of industry trends and emerging technologies in STA and related fields, and incorporate best practices into the team’s workflow
Prepare and present detailed timing reports and technical documentation to stakeholders
Foster a culture of innovation, collaboration, and continuous improvement within the STA team

Fulltime

Staff Engineer, ASIC Development Engineering (FPGA-RTL Design)

The FPGA design team, part of the (VHS) group is responsible for developing a wi...

Location

India , Bengaluru

Salary:

Not provided

Sandisk

Expiration Date

Until further notice

Requirements

B.Tech/M.Tech in Electrical Engineering, Computer Engineering, or equivalent
5 to 7 years of hands-on experience in RTL logic design
Strong SystemVerilog expertise
SV/UVM-based simulation knowledge is a plus
Experience in multi-clock, high-frequency, and high-performance digital designs
Familiarity with synthesis, STA, and optimization flows
FPGA development experience (Vivado / Synplify) is an advantage
Simulation and verification experience using NCSim, VCS, or equivalent tools
Knowledge of standard storage interfaces such as eMMC or UFS is a strong advantage
Scripting experience with Python/Perl for automation

Job Responsibility

Complex logic blocks & IPs design
Work in a multi-disciplinary environment with a variety of complex interfaces

Fulltime

Asic Engineer Sr Staff

Hewlett Packard Enterprise is seeking a seasoned Design-for-Test (DFT) Engineer ...

Location

United States , San Jose

Salary:

148000.00 - 340500.00 USD / Year

Hewlett Packard Enterprise

Expiration Date

Until further notice

Requirements

10+ years of hands-on DFT experience in ASIC design, preferably in networking or high-speed digital domains
deep understanding of fault models: stuck-at, transition, path-delay
expertise in scan compression, ATPG, and MBIST architecture
experience with Siemens Tessent tools: SSN, JTAG, IJTAG, MBIST, and memory repair
proficiency with Synopsys tools: DFT Compiler, DFTMAX, Tetramax, Design Compiler
simulation experience with Synopsys VCS and Cadence NC-Verilog
timing analysis using PrimeTime and Cadence Tempus
able to define test constraints and review STA reports to ensure timing closure in test modes
debugging with waveform tools such as Novas and SimVision
familiarity with ATE pattern formats (STIL, WGL) and JTAG SVF

Job Responsibility

define and implement DFT architecture for high-performance networking ASICs at 3nm and beyond
collaborate with RTL and physical design teams to integrate scan, compression, boundary scan, and MBIST features
develop and validate ATPG patterns for stuck-at, transition, and path-delay fault models
analyze and resolve DFT-related issues including ATPG DRC violations, simulation mismatches, and timing violations
apply test constraints and perform STA analysis to ensure timing closure in test modes
support silicon bring-up and ATE pattern validation using industry-standard formats (STIL, WGL, SVF)
conduct silicon failure analysis and contribute to system-level debug and yield improvement
automate DFT flows and analysis using scripting languages such as Perl and Tcl.

What we offer

health & wellbeing
personal & professional development
unconditional inclusion
competitive compensation, benefits, and career growth opportunities.

Fulltime

Staff Digital Design Engineer - DSP

This is an outstanding opportunity for an experienced engineer passionate about ...

Location

United Kingdom , Edinburgh

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

Proven experience in DSP algorithm development and implementation for SerDes, wireless communications or high-speed serial interfaces (Ethernet, PCIe, etc.)
Familiarity with equalization techniques such as FFE, CTLE, DFE or MLSE and their implementation
Strong background and experience in digital design techniques including clock domain crossing, RTL (preferably SystemVerilog), and ASIC front-end design tools and flows
Understanding of power analysis and techniques for optimization of digital designs for low power
Familiarity with simulation and modeling of DSP blocks in SerDes

Job Responsibility

Collaborate with architects, hardware, and verification engineers to refine and implement new DSP features for cutting-edge and next-generation SerDes transceivers with a focus on low power
Implement DSP algorithms for equalization, filtering and sequence detection
RTL development and using front-end ASIC tools (lint, synthesis, STA) to ensure the highest quality code
Develop comprehensive documentation detailing DSP algorithm interactions with SerDes hardware and software components

Fulltime

Staff Design Verification Engineer

We are looking for an adaptive, self-motivative Design Verification (DV) enginee...

Location

Singapore , Singapore

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

Excellent analytical and critical thinking skills along with attention to details
Must be an initiative-taker, able to drive tasks independently and efficiently to completion
Strong/effective communication skills
Enthusiastic team-first mentality
Ability to provide mentorship and guidance to junior engineers
Proven experience in design verification from specification to successful silicon
Experience in PLL, high-speed interfaces such as DDR, PCIe and high-speed SERDES
Experience in designs with multiple power domains
Experience in designs with multiple clock domains
Experience in behavior modeling for Analog Circuits

Job Responsibility

Analyze complex verification and digital design problems and propose verification / micro-architecture solutions
Develop RTL and Firmware validation
Drive/develop ASIC verification flows and scripts
Create Verification architecture
Work with the RTL Design team to ensure functional correctness and coverage
Support silicon bring-up and diagnostics
Support Post-silicon debug, root cause bug, provide solution or workaround

Resident Assistant

If you’re looking for a job that goes beyond the basics to deliver purpose and j...

Location

United States of America , Hillsboro

Salary:

18.00 - 20.00 USD / Hour

Leisure Care

Expiration Date

Until further notice

Requirements

Demonstrated experience in a caregiving role
Current CNA a plus!

Job Responsibility

Assists resident with activities of daily living (ADL's) and all personal care skills (bathing, dressing, grooming, toileting)
Makes appropriate observations about the resident’s condition in every interaction
Records and follows-up with changes in resident’s condition in a timely manner
Assists residents with laundry and housekeeping services as needed

What we offer

Medical, Dental and Vision
Early Wage Access (access to earned wages when needed!)
401k
10 days vacation & 1 hour Sick Leave earned for every 30 hours worked
Bereavement & Jury Duty Leave
6 Holidays
2 Float Holidays
Flexible Spending Accounts (Health and Dependent Care)
Meal Discounts
Tuition Assistance

Fulltime

Traffic Management CAD Technician

FM Conway is currently recruiting a Traffic Management CAD Technician to join ou...

Location

United Kingdom , Ipswich

Salary:

Not provided

360 Resourcing Solutions

Expiration Date

July 04, 2026

Requirements

Strong knowledge of Traffic Management operations
experience using CAD, BricsCAD and Cone 11 software
ability to read and translate blueprints and technical drawings
ability to work well under pressure, prioritise tasks effectively and have excellent attention to detail
M7 Lantra qualification is highly desirable, but not essential

Job Responsibility

Working within a team of Traffic Management development designers and Project Engineers to ensure that drawings are to a high and legal standard
Producing clear drawings, signage placement layouts and diversion route strategies
Developing safe and efficient traffic management plans for work sites and road network
Carrying out on site assessments as required
Designing sites in accordance with Chapter 8 TSM
Engaging with Project Teams & Engineers to respond effectively to working methods that require traffic Management designs that conform to a legal standard

What we offer

Career and professional development
23 days holiday plus bank holidays
Life assurance
Opportunities for internal and external training
Access to a wide range of shopping discounts through Rewarding Great People platform
Health and well-being benefits including 24-hour advice lines
Support from in-house mental health first aiders

Fulltime

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Staff Engineer, ASIC Development Engineering (STA)

Job Description

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