Staff Engineer, ASIC Development Engineering (STA)

• Own Subsystem level STA, providing direction and guidance to PnR team for Timing closure & Synthesis report analysis
• Work with IP & Design team for Timing constraints Development & Review activities
• Develop and implement advanced STA methodologies and strategies to meet the timing closure requirements of complex IC designs
• Collaborate with cross-functional teams, including design, verification, physical design, and DFT, to ensure seamless integration and optimal timing performance
• Drive the development and maintenance of STA scripts and tools to automate and streamline timing analysis processes
• Conduct thorough timing analysis, identify critical paths, and develop strategies to mitigate timing violations and improve overall design performance
• Stay abreast of industry trends and emerging technologies in STA and related fields, and incorporate best practices into the team’s workflow
• Prepare and present detailed timing reports and technical documentation to stakeholders
• Foster a culture of innovation, collaboration, and continuous improvement within the STA team

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field
• A minimum of 5 years of experience in Static Timing Analysis
• Proven track record of successfully executing STA
• In-depth knowledge of STA tools (e.g., Synopsys PrimeTime, Cadence Tempus, Constraints Manager) and methodologies
• Strong understanding of digital design principles, physical design, and semiconductor fabrication processes
• Excellent problem-solving skills and the ability to think strategically and analytically
• Exceptional communication and interpersonal skills, with the ability to effectively collaborate with cross-functional teams and stakeholders
• Ability to prioritize tasks and manage multiple project work simultaneously
• A proactive, results-oriented mindset with a passion for innovation and continuous improvement

Experience with advanced process nodes (e.g., 7nm, 5nm) is highly desirable