Staff Engineer, ASIC Development Engineering (Physical Design, Pnr, Floor Planning)

• Subsystem/block level ownership of Floorplanning, place and route flow for low power, high performance designs, debug of timing/power/area issues, clock tree analysis and assisting full chip timing convergence and timing closure
• Collaborate with cross-function teams, including design, DFT to streamline PNR process
• Drive IP integration strategies that ensure quality ASICs and avoid schedule surprises
• Conduct thorough design and timing analysis, identify critical paths, and develop strategies to mitigate timing violations and improve overall design convergence
• Stay abreast of industry trends and emerging technologies in PNR and related fields, and incorporate best practices into the team’s workflow
• Prepare and present detailed analysis, reports and technical documentation to stakeholders
• Foster a culture of innovation, collaboration, and continuous improvement within the PNR team

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field
• A minimum of 5 years of experience in Place and Route Domain
• Proven track record of successfully executing PNR
• In-depth knowledge of PNR tools (e.g., Synopsys Fusion Compiler, Cadence Innovus) and methodologies
• Strong understanding of digital design principles, physical design, and semiconductor fabrication processes
• Excellent problem-solving skills and the ability to think strategically and analytically
• Exceptional communication and interpersonal skills, with the ability to effectively collaborate with cross-functional teams and stakeholders
• Ability to prioritize tasks and manage multiple project work simultaneously
• A proactive, results-oriented mindset with a passion for innovation and continuous improvement
• Experience with advanced process nodes (e.g., 7nm, 5nm) is highly desirable

Experience with advanced process nodes (e.g., 7nm, 5nm)