Staff Engineer - ASIC Development Engineering (DFT) Job at Sandisk (Bangalore)

Staff Engineer, ASIC Development Engineering

Are you ready to push the boundaries of what's possible in technology? Join the ...

Location

India , Bengaluru

Salary:

Not provided

Sandisk

Expiration Date

Until further notice

Requirements

Bachelor’s or master’s degree in electrical engineering, Computer Engineering, or a related field with 5-8 years of experience
Proven experience in ASIC RTL design, with a strong grasp of Verilog/System Verilog
Strong understanding of SoC architecture, AMBA protocols (AXI/AHB/APB), interconnects and peripherals for debug
Prior knowledge of Power Intent format (UPF) and Timing Constraints (SDC) is a must
Proficiency in scripting languages (e.g., Python, TCL) for automation
Hands-on with EDA tools (simulation, lint, CDC, synthesis, formal verification)
Strong problem-solving skills and the ability to thrive in a dynamic environment
Excellent communication and teamwork abilities

Job Responsibility

Innovate and develop RTL code for complex ASICs
Contribute in SoC subsystems related to CPU complex, DDR, Host, Flash, Debug, Clocks, resets, Power domains etc. for top of the line flash controllers
Ensure robust design methodologies including Lint, CDC, RDC, CLP and FC-Elab
Utilize advanced AI-driven tools, including GitHub Copilot, to streamline the design process
Collaborate with DFT, PD, Hardware and Firmware teams for delivering the most optimal solution
Work along side with the SoC Managers and SoC Leads to deliver best-in-class solution
Stay abreast of the latest industry trends and emerging technologies in AI and ASIC design

Fulltime

Asic Engineer Sr Staff

Hewlett Packard Enterprise is seeking a seasoned Design-for-Test (DFT) Engineer ...

Location

United States , San Jose

Salary:

148000.00 - 340500.00 USD / Year

Hewlett Packard Enterprise

Expiration Date

Until further notice

Requirements

10+ years of hands-on DFT experience in ASIC design, preferably in networking or high-speed digital domains
deep understanding of fault models: stuck-at, transition, path-delay
expertise in scan compression, ATPG, and MBIST architecture
experience with Siemens Tessent tools: SSN, JTAG, IJTAG, MBIST, and memory repair
proficiency with Synopsys tools: DFT Compiler, DFTMAX, Tetramax, Design Compiler
simulation experience with Synopsys VCS and Cadence NC-Verilog
timing analysis using PrimeTime and Cadence Tempus
able to define test constraints and review STA reports to ensure timing closure in test modes
debugging with waveform tools such as Novas and SimVision
familiarity with ATE pattern formats (STIL, WGL) and JTAG SVF

Job Responsibility

define and implement DFT architecture for high-performance networking ASICs at 3nm and beyond
collaborate with RTL and physical design teams to integrate scan, compression, boundary scan, and MBIST features
develop and validate ATPG patterns for stuck-at, transition, and path-delay fault models
analyze and resolve DFT-related issues including ATPG DRC violations, simulation mismatches, and timing violations
apply test constraints and perform STA analysis to ensure timing closure in test modes
support silicon bring-up and ATE pattern validation using industry-standard formats (STIL, WGL, SVF)
conduct silicon failure analysis and contribute to system-level debug and yield improvement
automate DFT flows and analysis using scripting languages such as Perl and Tcl.

What we offer

health & wellbeing
personal & professional development
unconditional inclusion
competitive compensation, benefits, and career growth opportunities.

Fulltime

Staff Engineer, ASIC Development Engineering

Are you ready to push the boundaries of what's possible in technology? Join the ...

Location

India , Bangalore

Salary:

Not provided

Sandisk

Expiration Date

Until further notice

Requirements

Bachelor’s or master’s degree in electrical engineering, Computer Engineering, or a related field with 5-8 years of experience
Proven experience in ASIC RTL design, with a strong grasp of Verilog/System Verilog
Strong understanding of SoC architecture, AMBA protocols (AXI/AHB/APB), interconnects and peripherals for debug
Prior knowledge of Power Intent format (UPF) and Timing Constraints (SDC) is a must
Proficiency in scripting languages (e.g., Python, TCL) for automation
Hands-on with EDA tools (simulation, lint, CDC, synthesis, formal verification)
Strong problem-solving skills and the ability to thrive in a dynamic environment
Excellent communication and teamwork abilities

Job Responsibility

Innovate and develop RTL code for complex ASICs
Contribute in SoC subsystems related to CPU complex, DDR, Host, Flash, Debug, Clocks, resets, Power domains etc. for top of the line flash controllers
Ensure robust design methodologies including Lint, CDC, RDC, CLP and FC-Elab
Utilize advanced AI-driven tools, including GitHub Copilot, to streamline the design process
Collaborate with DFT, PD, Hardware and Firmware teams for delivering the most optimal solution
Work along side with the SoC Managers and SoC Leads to deliver best-in-class solution
Stay abreast of the latest industry trends and emerging technologies in AI and ASIC design

Fulltime

Staff Engineer, ASIC Development Engineering (STA)

We are seeking a highly skilled and experienced Staff Engineer for our Static Ti...

Location

India , Bengaluru

Salary:

Not provided

Sandisk

Expiration Date

Until further notice

Requirements

Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field
A minimum of 5 years of experience in Static Timing Analysis
Proven track record of successfully executing STA
In-depth knowledge of STA tools (e.g., Synopsys PrimeTime, Cadence Tempus , Constraints Manager) and methodologies
Strong understanding of digital design principles, physical design, and semiconductor fabrication processes
Excellent problem-solving skills and the ability to think strategically and analytically
Exceptional communication and interpersonal skills, with the ability to effectively collaborate with cross-functional teams and stakeholders
Ability to prioritize tasks and manage multiple project work simultaneously
A proactive, results-oriented mindset with a passion for innovation and continuous improvement
Experience with advanced process nodes (e.g., 7nm, 5nm) is highly desirable

Job Responsibility

Own Subsystem level STA , providing direction and guidance to PnR team for Timing closure & Synthesis report analysis
Work with IP & Design team for Timing constraints Development & Review activities
Develop and implement advanced STA methodologies and strategies to meet the timing closure requirements of complex IC designs
Collaborate with cross-functional teams, including design, verification, physical design, and DFT, to ensure seamless integration and optimal timing performance
Drive the development and maintenance of STA scripts and tools to automate and streamline timing analysis processes
Conduct thorough timing analysis, identify critical paths, and develop strategies to mitigate timing violations and improve overall design performance
Stay abreast of industry trends and emerging technologies in STA and related fields, and incorporate best practices into the team’s workflow
Prepare and present detailed timing reports and technical documentation to stakeholders
Foster a culture of innovation, collaboration, and continuous improvement within the STA team

Fulltime

New

Senior/Associate Quantity Surveyor

A well-established, independent property and construction consultancy is seeking...

Location

United Kingdom , London

Salary:

75000.00 - 80000.00 GBP / Year

Brandon James

Expiration Date

Until further notice

Requirements

Degree qualified in Quantity Surveying or a related construction discipline
Ideally MRICS or actively working towards chartership
Proven experience as a Senior Quantity Surveyor or Associate in a consultancy environment
Strong technical knowledge across cost planning, procurement, and contract administration
Project experience across sectors such as residential, education, healthcare, and commercial
Excellent communication skills and confident in a client-facing role
Commercially focused, proactive, and organised

Job Responsibility

Deliver full pre- and post-contract Quantity Surveying services
Prepare cost plans, budgets, tender documentation, and procurement strategies
Lead tender processes and contractor selection
Administer contracts and manage change control
Monitor project costs and produce accurate financial reports
Provide value engineering and cost-saving advice
Support and mentor junior surveyors towards chartership

What we offer

23 days annual leave
Hybrid working
Private medical insurance
Enhanced pension contribution
Life assurance
Bonus scheme
Professional development & CPD support
Mental health and wellbeing initiatives
Regular social and networking events

Fulltime

New

Senior Full Stack Developer

PAUL Tech AG is a technology leader in the real estate industry with the mission...

Location

Germany , Mannheim

Salary:

Not provided

PAUL Tech AG

Expiration Date

Until further notice

Requirements

Strong understanding of flexible front-end and back-end architectures
Proficiency in JavaScript, Node.js, ReactJS/Vue.js, HTML5, CSS, and Redux
Experience with RESTful APIs, WebSockets, and databases (Neo4j, MongoDB, etc.)
Hands-on experience with CI/CD pipeline configuration and integration
Strong testing mindset with experience in unit, integration, and end-to-end testing
Self-organized, proactive, and capable of taking ownership of tasks
Very good German and English language skills

Job Responsibility

Develop and Implement Solutions
Analyze requirements, design, and develop back-end and front-end frameworks
Ensure seamless integration of Master Data Management and IoT infrastructure
Quality and Best Practices
Apply best practices in development, testing, debugging, and documentation
Ensure high-quality deployment through CI/CD pipelines
Collaboration and Innovation
Work closely with a team of visionaries to challenge and refine new ideas
Drive framework-driven development for web and mobile applications
Continuous Improvement

What we offer

A meaningful job that contributes to global CO2 savings
A collegial working atmosphere with short decision paths
A permanent contract with an above-average salary
30 days vacation per calendar year plus 24.12. and 31.12. off
Company private health insurance and supplementary pension
Company fitness subsidy in your region
Regular company events to which you are very welcome
Tram ticket as well as drinks and fruit in our offices

Fulltime

New

Tax officer

Semi-Qualified Chartered Accountant / CA Fresher – Taxation role in the Finance ...

Location

India , Mumbai

Salary:

Not provided

Randstad

Expiration Date

February 02, 2026

Requirements

Semi-Qualified Chartered Accountant (CA Inter) with 4–6 years of experience in direct and indirect tax
CA Fresher with strong article-ship exposure
Skilled in GST compliance, Income Tax filings, e-invoicing, reconciliations, and audit documentation
Experienced in working within pharma/manufacturing environments with strong system and coordination capabilities
Core Competencies: GST Compliance (GSTR-1/3B/9/9C)
TDS & Income Tax Filings
E-invoicing & E-way Bill Management
Tax Audit & Assessment Support
Litigation Documentation
Reconciliations (2B vs Books, TDS, ERP vs Portal)

Job Responsibility

Filing of GST returns, TDS returns, and income tax-related compliances
Preparation of data, workings, and documentation for tax audits, assessments, and litigation
Management of e-invoicing, e-way bill generation, and GST registration updates across portals
Coordination with consultants, vendors, and internal teams for smooth compliance
Tracking GST notifications, circulars, and assisting Tax Lead with regulatory impact assessment
Maintaining compliance trackers, audit-ready documentation, and statutory reconciliations
Preparing responses to notices and assisting in departmental proceedings for GST and Income Tax

What we offer

Structured learning
Cross-functional exposure
Growth in end-to-end taxation
Opportunity to work closely with Tax Lead & external advisors, accelerating technical growth
Experience in SAP-based tax configuration, automation tools, and process optimization
Involvement in assessment proceedings, litigation support, refund applications, and audit submissions
Fast-track path for CA freshers towards Assistant Manager – Taxation roles

Fulltime

New

Assistant Manager

Interested in an excellent opportunity to get your foot in the door with one of ...

Location

United States , Appleton

Salary:

20.15 - 21.15 USD / Hour

Hobby Lobby

Expiration Date

Until further notice

Requirements

Excellent Customer Service Skills
Good With Merchandise Displays
Basic Computer Skills
Desire To Learn
Trustworthy And Dependable
Previous Work References
Some Previous Management Experience Preferred

What we offer

Competitive Wages
Medical, Dental and Prescription Benefits
401(k) Program with Company Match
Paid Vacation
Sick / Personal Pay (SPP)
Employee Discount
Life Insurance and Long Term Disability Insurance (LTD)
Flexible Spending Plan
Holiday Pay

Fulltime

Staff Engineer - ASIC Development Engineering (DFT)

Sandisk

Location:
India , Bangalore

Category:
IT - Software Development

Contract Type:
Not provided

Salary:

Job Description:

Job Responsibility:

Requirements:

Additional Information:

Job Posted:
December 11, 2025

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