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As a Staff level Design Engineer you will focus on the research, development and productization of parameterized IP for inclusion to AMD IP libraries targeting AMD FPGA hardware.
Job Responsibility:
Research, design, development and productization of DSP and linear algebra IP solutions which target AMD FPGA programmable logic and AMD AIE array processors
Verification and validation of these designs
Collaboration with peer teams
Collaboration for continuous improvement of internal processes and techniques
Requirements:
Proficient in HDL, design capture and metadata languages (VHDL, System Verilog, C/C++, Python, TCL)
Proficient in Digital Signal processing and Linear Algebra
Expert in digital design techniques, especially for high speed
Experience in digital design, Digital Signal Processing, Linear Algebra
Experience in GIT, Perforce, Unix, LSF
Familiarity with scripting languages such as Python, Perl, Tcl
Bachelors, Masters or PhD in Computer Engineering, Computer Science or Electrical and Electronic Engineering