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This is an outstanding opportunity for an experienced engineer passionate about digital signal processing (DSP) algorithms and their application in high-speed SerDes (Serializer/Deserializer) systems. As part of a team, you will optimize and implement advanced DSP algorithms and circuits for 200+Gbps SerDes, with a strong focus on power efficiency and optimization. Your work will directly impact the performance and robustness of AMD's next-generation connectivity solutions for markets such as data center networking, wireless telecommunications, and aerospace/defense.
Job Responsibility:
Collaborate with architects, hardware, and verification engineers to refine and implement new DSP features for cutting-edge and next-generation SerDes transceivers with a focus on low power
Implement DSP algorithms for equalization, filtering and sequence detection
RTL development and using front-end ASIC tools (lint, synthesis, STA) to ensure the highest quality code
Develop comprehensive documentation detailing DSP algorithm interactions with SerDes hardware and software components
Requirements:
Proven experience in DSP algorithm development and implementation for SerDes, wireless communications or high-speed serial interfaces (Ethernet, PCIe, etc.)
Familiarity with equalization techniques such as FFE, CTLE, DFE or MLSE and their implementation
Strong background and experience in digital design techniques including clock domain crossing, RTL (preferably SystemVerilog), and ASIC front-end design tools and flows
Understanding of power analysis and techniques for optimization of digital designs for low power
Familiarity with simulation and modeling of DSP blocks in SerDes