Staff DFT Engineer

• Responsible for Defining, Developing and Implementing DFT methodologies for a high-performance LiDAR Chip
• Owning DFT planning, Insertion, verification and validation
• Collaborating with RTL Design, Physical Design teams and ASIC vendors to ensure proper test implementation for automotive grade SoC
• Work closely with IP vendors on proper DFT Implementation of the IPs in SoC
• Supporting post-silicon bring-up and debug including silicon failure analysis and yield improvement
• Create and maintain documentation, DFT guidelines and test architecture specification

• 12+ Years of experience in developing and implementing DFT architecture and test strategies for complex ASIC/SoC Designs
• In-Depth knowledge and hands-on experience of industry standard and proprietary DFT techniques, such as, SCAN/ATPG, Built-in-Self Test (MBIST/LBIST) Architecture , JTAG (IEEE 1149.x/1500/1687), Boundary Scan (BSCAN) and compression/decompression technologies on Digital and Mixed Signal SoCs
• In-Depth knowledge of EDA tools used for DFT, especially Mentor/Synopsys tools
• Scripting expertise in Python/PERL, TCL, etc
• Experience in RTL coding and SDC creation for DFT Modes
• Recent Tapeout experience in advanced nodes

Familiarity with developing automotive grade silicon with AEC-Q100 qualification and ISO26262