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AMD is looking for an experienced Design Verification Engineer willing to take on the challenge of verifying a leading edge PCIe Controller Sub-System Design. In this role you will be given an opportunity to work on the next generation Power optimization technology that will be part of future AMD SOCs powering AI Training and Inference, Gaming Consoles, Servers and Personal Computers as well as Graphics Cards and VR sets. This team is responsible for the Verification of several critical blocks, interoperability of lower level IPs and the SubSystem delivery to SoC. The team is tasked with verifying a balanced architecture between power consumption and performance, delivering high complexity RTL code and Verification components, as well as creating advanced testbenches using leading-edge verification techniques.
Job Responsibility
Work on functional or Power verification execution from test plan to verification signoff
Collaborate with architects and designers to understand the IP features
Write/Implement/Review Test Plans
Verification of critical high speed digital designs using both coverage driven random and directed testing techniques as well as Formal verification
Own some or all aspects of the Verification flow from initial test planning to coverage convergence and sign-off closure for one or more features and aspects of SubSystem level IP interoperability
Build testbench components and develop test and sequence libraries, by applying Objected Oriented Programming Verification techniques following UVM methodology
Conduct and participate in Code Reviews
Technical leadership, including block ownership from start to finish and verification sign-off
Requirements
Bachelors or Masters degree in Electronics/Computer/Electrical Engineering
7+ years of relevant DV experience
Expert in SystemVerilog, UVM
Proficient in object-oriented programming, scripting (Ruby, Python, Perl), and low-level programming languages
Experience with Low Power verification techniques and UPF flow
PC System Architecture: PCI Express, SATA, USB, Ethernet, HyperTransport, DDR
Excellent knowledge of standard bus/interface protocols (i.e., AXI, AHB, AMBA, OCP, PIPE)
Exposure to AI implementation to improve verification flows
Experience with simulation profiling, efficiency improvements, acceleration, HLS tools/process
Must be a self-starter, and able to drive independently and efficiently challenge time-critical tasks to on-time completion
Strong communication, time management, and presentation skills
Scripting language experience: Perl, Ruby, Makefile, shell preferred
Proven experience in verifying commercially successful IPs, Subsystems and or SoCs
Strong ability to provide mentorship and guidance to junior and senior engineers, a very effective team player, must have strong technical skills and provide a positive influence on team morale and culture