Staff Design Engineer Jobs

Aeva

Location:
India, Bangalore

Category:
IT - Software Development

Contract Type:
Not provided

Salary:

Not provided

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Job Description:

As a key player on the Digital Design team, you will participate in the RTL design and development of the signal processing path for Aeva’s 4-D Lidar processing chip. You will be responsible for implementing and/or integrating sub-components of the design in ASICs and FPGAs.

Job Responsibility:

Develop custom sub-components of the digital signaling pipeline like filters, FFTs, control logic, etc.
Write micro-architecture specifications, Code RTL, Test & Validate Aeva-specific sub-components
Implement additional functionality including functional safety and robustness functions
Focus on developing efficient, highly reliable, highly available, robust functionality
Work with Architects, design engineers, verification engineers, and System software teams to ensure that the SOC meets its functional, performance, and power targets

Requirements:

10+ years of experience in the design of DSP designs, algorithms, and signal processing functionality in ASICs/FPGAs
Ability to achieve high performance and low power targets
Experience writing System Verilog RTL Code
Working experience and knowledge in AMBA protocols
Desire to learn & implement groundbreaking new processes and methodology for continuous improvement

Nice to have:

Matlab/NumPy/C/C++
Working experience and knowledge in LPDDR, Ethernet, MIPI, and high-speed Serdes etc.
Experience in FPGA designs, pre-silicon validation on emulation platforms such as Cadence Palladium, Mentor Veloce, Synopsys Zebu
Post-silicon bring-up and validation planning and execution
Diagnostics Firmware development and validation

Additional Information:

Job Posted:
December 05, 2025

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Staff Design Engineer