STA Expert Engineer R&D

• Timing constraints generation for ASIC flow (Using for synthesis, PNR and sign-off analysis)
• In charge of timing analysis tool settings for timing closure and sign-off settings before tape-out
• Perform STA Sign-off at top level
• Work in close relationship with logical design, physical design and flow teams

• Bac + 5, Engineering degree or equivalent, with a specialization in micro-electronics and/or integrated circuits
• At least 5 years of experience in timing constraints generation and timing convergence
• Expertise in timing analysis tools Synopsys and/or Cadence (PrimeTime, Tempus Timing Sign-off Solution)
• Familiarity with all methodologies of timing closure
• Knowledge of ASIC design flow (RTL, DFT, equivalence checking and place and route flow)
• Good experience of Clock Domain Crossing (CDC) timing issues and specifics timing exceptions (Multi cycle path, false path, max delay, min delay ….)
• Good knowledge of modes/corners, OCV, AOCV and POCV concept, noise and cross-talk effects on timing in advanced process technology nodes (16nm and below)
• Very good experience in using TCL language
• Good experience in Perl and/or Python languages
• Good experience in using revision control tool (Git…)
• Fluent English (collaboration with English-spoken engineers)

Knowledge of low power techniques including clock gating, power gating and multi-voltage designs would be a plus